cpldfit: version H.42 Xilinx Inc.
Fitter Report
Design Name: sw2_pld_main Date: 6-13-2006, 3:43PM
Device Used: XCR3256XL-12-PQ208
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
219/256 ( 86%) 541 /768 ( 70%) 519 /640 ( 81%) 127/256 ( 50%) 116/160 ( 72%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO GCK
Block Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
FB1 11/16 29/40 48/48* 6/10 1/2
FB2 11/16 35/40 48/48* 4/10 1/2
FB3 10/16 36/40 48/48* 9/10 1/2
FB4 14/16 38/40* 48/48* 6/ 9 1/2
FB5 16/16* 34/40 47/48 9/ 9* 1/2
FB6 16/16* 15/40 16/48 10/10* 1/2
FB7 9/16 38/40* 48/48* 0/10 1/2
FB8 16/16* 22/40 21/48 9/10 1/2
FB9 16/16* 38/40* 39/48 7/10 1/2
FB10 16/16* 37/40 40/48 4/10 1/2
FB11 16/16* 36/40 33/48 7/ 9 1/2
FB12 16/16* 27/40 23/48 10/10* 1/2
FB13 16/16* 26/40 18/48 10/10* 1/2
FB14 13/16 38/40* 17/48 3/ 9 0/2
FB15 11/16 37/40 31/48 5/10 1/2
FB16 12/16 33/40 16/48 7/10 0/2
----- ------- ------- -----
Total 219/256 519/640 541/768 106/156
* - Resource is exhausted
** Local Control Term Resources **
LCT0 LCT1 LCT2 LCT3 LCT4 LCT5 LCT6 LCT7
FB1 oe clk clk
FB2 oe clk
FB3
FB4
FB5 uct1
FB6 uct2
FB7 clk
FB8 uct4
FB9 clk
FB10
FB11
FB12
FB13
FB14 clk
FB15 clk
FB16 clk clk
Legend:
ce - clock enable
clk - clock
oe - output enable
sr - set/reset
uct1 - universal control term clock
uct2 - universal control term output enable
uct3 - universal control term preset
uct4 - universal control term reset
LCT0 - oe and/or sr can be mapped to this local control term
LCT1 - oe and/or sr can be mapped to this local control term
LCT2 - oe and/or sr can be mapped to this local control term
LCT3 - sr can be mapped to this local control term
LCT4 - ce and/or clk and/or sr can be mapped to this local control term
LCT5 - clk and/or sr can be mapped to this local control term
LCT6 - clk and/or oe can be mapped to this local control term
LCT7 - clk can be mapped to this local control term
** Global Control Resources **
GCK UCLK UOE UPST URST
Used/Tot Used/Tot Used/Tot Used/Tot Used/Tot
1/4 1/1 1/1 0/1 1/1
GCK - Global Clock
UCLK - Universal Control Term Clock
UOE - Universal Control Term Output Enable
UPST - Universal Control Term Preset
URST - Universal Control Term Reset
Signal 'CLK' mapped onto global clock net GCK0.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|-------------------------------------
Input : 9 9 | I/O : 115 156
Output : 50 50 | GCK/I : 1 4
Bidirectional : 56 56 |
GCK : 1 1 |
---- ----
Total 116 116
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 28 and input limit: 28
WARNING:Cpld - Unable to map all desired signals into function block, FB3.
Buffering output signal post_sleep to allow all signals assigned to this
function block to be placed.
WARNING:Cpld - Unable to map all desired signals into function block, FB3.
Buffering output signal row_pulse to allow all signals assigned to this
function block to be placed.
WARNING:Cpld - Unable to map all desired signals into function block, FB3.
Buffering output signal SAN to allow all signals assigned to this function
block to be placed.
WARNING:Cpld:829 - Signal 'dsp_data<9>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<8>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<31>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<30>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<29>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<28>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<27>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<26>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<25>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<24>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<23>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<22>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<21>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<20>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<19>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<18>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<17>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<16>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<15>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<14>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<13>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<12>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<11>_MC.TRST' has been minimized to 'GND'.
WARNING:Cpld:829 - Signal 'dsp_data<10>_MC.TRST' has been minimized to 'GND'.
************************* Summary of Mapped Logic ************************
** 106 Outputs **
Signal Total Total Loc Pin Pin Pin Slew Reg Init
Name Pts Inps No. Type Use Rate State
dsp_data<2> 3 3 FB1_1 6 I/O I/O FAST RESET
dsp_data<3> 3 3 FB1_2 7 I/O I/O FAST RESET
dsp_data<4> 2 2 FB1_3 8 I/O I/O FAST RESET
dsp_data<5> 2 2 FB1_4 9 I/O I/O FAST RESET
dsp_data<6> 2 2 FB1_5 10 I/O I/O FAST RESET
dsp_data<7> 2 2 FB1_12 11 I/O I/O FAST RESET
dsp_data<1> 3 3 FB2_1 4 I/O I/O FAST RESET
dsp_data<0> 3 3 FB2_2 3 I/O I/O FAST RESET
data<0> 2 1 FB2_15 199 I/O O FAST
data<1> 2 1 FB2_16 198 I/O O FAST
PRE 5 8 FB3_2 18 I/O O FAST RESET
SAN 1 1 FB3_3 19 I/O O FAST
pre_sleep 2 2 FB3_4 20 I/O O FAST RESET
imp_slp 0 0 FB3_5 21 I/O O FAST
post_sleep 1 1 FB3_12 22 I/O O FAST
row_pulse 1 1 FB3_13 24 I/O O FAST
row_clk 11 17 FB3_14 25 I/O O FAST RESET
col_clk 11 21 FB3_15 26 I/O O FAST RESET
sel_clk 21 27 FB3_16 27 I/O O FAST RESET
data<2> 3 3 FB4_1 197 I/O O FAST
data<3> 3 3 FB4_2 196 I/O O FAST
data<4> 2 2 FB4_3 195 I/O O FAST
data<5> 3 3 FB4_4 194 I/O O FAST
data<6> 3 3 FB4_5 193 I/O O FAST
data<7> 3 3 FB4_12 192 I/O O FAST
col_pulse 3 7 FB5_1 28 I/O O FAST RESET
sel_pulse 9 19 FB5_2 29 I/O O FAST RESET
wr_clk_en 0 0 FB5_4 31 I/O O FAST
comp_sleep 3 7 FB5_5 33 I/O O FAST RESET
SH_samp_0 3 7 FB5_12 34 I/O O FAST RESET
SH_samp_1 0 0 FB5_13 35 I/O O FAST
SH_samp_2 0 0 FB5_14 36 I/O O FAST
SH_samp_3 0 0 FB5_15 37 I/O O FAST
VREG_EN_l 0 0 FB5_16 38 I/O O FAST
chip_sel<12> 0 0 FB6_1 78 I/O O FAST
data<21> 2 2 FB6_2 77 I/O I/O FAST
data<22> 2 2 FB6_3 76 I/O I/O FAST
data<23> 2 2 FB6_4 73 I/O I/O FAST
data<24> 2 2 FB6_5 71 I/O I/O FAST
data<25> 2 2 FB6_12 70 I/O I/O FAST
Signal Total Total Loc Pin Pin Pin Slew Reg Init
Name Pts Inps No. Type Use Rate State
data<26> 2 2 FB6_13 69 I/O I/O FAST
data<27> 2 2 FB6_14 68 I/O I/O FAST
data<28> 2 2 FB6_15 67 I/O I/O FAST
data<29> 2 2 FB6_16 66 I/O I/O FAST
data<30> 2 1 FB8_1 65 I/O I/O FAST
data<31> 2 1 FB8_2 64 I/O I/O FAST
rb_pd_l 0 0 FB8_3 62 I/O O FAST
dac_clk 1 1 FB8_4 61 I/O O FAST
dac_cs_l 0 0 FB8_5 60 I/O O FAST
dac_pd 0 0 FB8_12 59 I/O O FAST
dac_en 2 3 FB8_13 58 I/O O FAST RESET
cntr_8 3 7 FB8_14 57 I/O O FAST RESET
cntr_9 3 7 FB8_15 56 I/O O FAST RESET
data<15> 2 1 FB9_4 160 I/O I/O FAST
data<14> 2 1 FB9_5 161 I/O I/O FAST
data<13> 2 1 FB9_12 162 I/O I/O FAST
data<12> 2 1 FB9_13 163 I/O I/O FAST
data<11> 2 1 FB9_14 164 I/O I/O FAST
data<10> 2 1 FB9_15 166 I/O I/O FAST
data<9> 3 3 FB9_16 167 I/O I/O FAST
dsp_data<8> 2 1 FB10_13 145 I/O I/O FAST RESET
dsp_data<9> 2 1 FB10_14 144 I/O I/O FAST RESET
dsp_data<10> 2 1 FB10_15 142 I/O I/O FAST RESET
dsp_data<11> 2 1 FB10_16 141 I/O I/O FAST RESET
data<8> 3 3 FB11_1 168 I/O I/O FAST
chip_sel<5> 0 0 FB11_2 169 I/O O FAST
chip_sel<6> 0 0 FB11_3 170 I/O O FAST
chip_sel<3> 0 0 FB11_4 171 I/O O FAST
chip_sel<4> 0 0 FB11_5 172 I/O O FAST
chip_sel<1> 17 26 FB11_12 173 I/O O FAST RESET
chip_sel<2> 0 0 FB11_13 175 I/O O FAST
dsp_data<12> 2 1 FB12_1 140 I/O I/O FAST RESET
dsp_data<13> 2 1 FB12_2 139 I/O I/O FAST RESET
dsp_data<14> 2 1 FB12_3 138 I/O I/O FAST RESET
dsp_data<15> 2 1 FB12_4 137 I/O I/O FAST RESET
dsp_data<16> 2 1 FB12_5 136 I/O I/O FAST RESET
dsp_data<17> 2 1 FB12_12 135 I/O I/O FAST RESET
dsp_data<18> 2 1 FB12_13 133 I/O I/O FAST RESET
dsp_data<19> 2 1 FB12_14 132 I/O I/O FAST RESET
dsp_data<20> 2 1 FB12_15 131 I/O I/O FAST RESET
Signal Total Total Loc Pin Pin Pin Slew Reg Init
Name Pts Inps No. Type Use Rate State
dsp_data<21> 2 1 FB12_16 130 I/O I/O FAST RESET
chip_sel<11> 0 0 FB13_1 79 I/O O FAST
chip_sel<10> 0 0 FB13_2 80 I/O O FAST
chip_sel<9> 0 0 FB13_3 81 I/O O FAST
chip_sel<8> 0 0 FB13_4 84 I/O O FAST
chip_sel<7> 0 0 FB13_5 86 I/O O FAST
data<20> 2 1 FB13_12 87 I/O I/O FAST
data<19> 2 1 FB13_13 88 I/O I/O FAST
data<18> 2 1 FB13_14 89 I/O I/O FAST
data<17> 2 1 FB13_15 90 I/O I/O FAST
data<16> 2 1 FB13_16 91 I/O I/O FAST
dsp_data<22> 2 1 FB14_1 129 I/O I/O FAST RESET
dsp_data<23> 2 1 FB14_2 128 I/O I/O FAST RESET
dsp_data<24> 2 1 FB14_4 126 I/O I/O FAST RESET
off_adj 0 0 FB15_1 92 I/O O FAST
off_adj_delay 0 0 FB15_2 93 I/O O FAST
transmit 3 15 FB15_5 97 I/O O FAST RESET
status_reg_load_out 2 6 FB15_14 100 I/O O FAST RESET
rec_prot 0 0 FB15_16 102 I/O O FAST
dsp_data<31> 2 1 FB16_3 115 I/O I/O FAST RESET
dsp_data<30> 2 1 FB16_4 114 I/O I/O FAST RESET
dsp_data<29> 2 1 FB16_5 113 I/O I/O FAST RESET
dsp_data<28> 2 1 FB16_12 112 I/O I/O FAST RESET
dsp_data<27> 2 1 FB16_13 111 I/O I/O FAST RESET
dsp_data<26> 2 1 FB16_14 110 I/O I/O FAST RESET
dsp_data<25> 2 1 FB16_15 109 I/O I/O FAST RESET
** 113 Buried Nodes **
Signal Total Total Loc Reg Init
Name Pts Inps State
FSM/SHELL1_DSP_SM_2/col_cnt1 5 14 FB1_7 RESET
status_reg_data<3> 12 19 FB1_8 RESET
status_reg_load 13 20 FB1_9 RESET
status_reg_data<0> 11 14 FB1_10 RESET
status_reg_data<2> 9 14 FB1_11 RESET
N_PZ_4399 5 14 FB2_6
FSM/SHELL1_DSP_SM_2/row_cnt0 4 13 FB2_7 RESET
FSM/SHELL1_DSP_SM_2/row_cnt1 4 14 FB2_8 RESET
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 11 21 FB2_9 RESET
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 11 19 FB2_10 RESET
status_reg_data<1> 10 11 FB2_11 RESET
FSM/SHELL1_DSP_SM_2/col_cnt2 5 14 FB2_14 RESET
N_PZ_4299 1 4 FB3_11
cntr_cnt<7> 2 9 FB4_6 RESET
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 10 18 FB4_7 RESET
FSM/SHELL1_DSP_SM_2/cntr_rst 14 25 FB4_8 RESET
demux_chip_sel_tri<2> 4 16 FB4_9 RESET
demux_chip_sel_tri<1> 4 16 FB4_10 RESET
demux_chip_sel_tri<0> 4 16 FB4_11 RESET
demux_chip_sel_tri<3> 3 14 FB4_14 RESET
FSM/SHELL1_DSP_SM_2/todsp_command0 3 9 FB4_16 RESET
cntr_set_value<3> 7 16 FB5_3 RESET
FSM/SHELL1_DSP_SM_2/sel_cnt3 7 11 FB5_6 RESET
FSM/SHELL1_DSP_SM_2/sel_cnt2 7 11 FB5_7 RESET
N_PZ_4460 1 9 FB5_8
cntr_tri 9 14 FB5_9 RESET
N_PZ_4112 4 12 FB5_10
FSM/SHELL1_DSP_SM_2/ramp_cnt0 7 14 FB5_11 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt6 2 6 FB6_6 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt5 2 5 FB6_7 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt4 2 4 FB6_8 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt3 2 3 FB6_9 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt2 2 2 FB6_10 RESET
FSM/SHELL1_DSP_SM_2/ramp_cnt1 2 1 FB6_11 RESET
FSM/SHELL1_DSP_SM_2/sel_cnt0 6 14 FB7_6 RESET
FSM/SHELL1_DSP_SM_2/col_cnt5 8 14 FB7_7 RESET
FSM/SHELL1_DSP_SM_2/col_cnt4 7 14 FB7_8 RESET
FSM/SHELL1_DSP_SM_2/col_cnt3 6 14 FB7_9 RESET
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 10 23 FB7_10 RESET
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 12 28 FB7_11 RESET
Signal Total Total Loc Reg Init
Name Pts Inps State
N_PZ_4093 2 4 FB7_14
row_pulse_BUFR 5 14 FB7_15 RESET
post_sleep_BUFR 6 16 FB7_16 RESET
cntr_set_value<6> 4 8 FB8_6 RESET
cntr_set_value<5> 3 7 FB8_7 RESET
cntr_set_value<2> 3 7 FB8_8 RESET
cntr_set_value<0> 3 7 FB8_9 RESET
FSM/SHELL1_DSP_SM_2/ramps0 3 6 FB8_10 RESET
FSM/SHELL1_DSP_SM_2/ramps1 3 8 FB8_11 RESET
cntr_set_value<7> 3 8 FB8_16 RESET
N_PZ_4387 2 12 FB9_1
N_PZ_4401 5 13 FB9_2
SAN_BUFR 10 18 FB9_3 RESET
FSM/SHELL1_DSP_SM_2/sel_cnt1 5 9 FB9_6 RESET
FSM/SHELL1_DSP_SM_2/todsp_command1 3 9 FB9_7 RESET
N_PZ_4192 2 7 FB9_8
sample_reg_load 4 7 FB9_9 RESET
cntr_set_value<1> 4 6 FB9_10 RESET
cntr_sel 2 2 FB9_11 RESET
FSM/SHELL1_DSP_SM_2/tochip_command1 5 12 FB10_1 RESET
FSM/SHELL1_DSP_SM_2/tochip_command0 5 9 FB10_2 RESET
N_PZ_4127 2 5 FB10_3
N_PZ_4398 2 4 FB10_4
N_PZ_4283 2 5 FB10_5
N_PZ_4190 2 8 FB10_6
N_PZ_4126 4 9 FB10_7
N_PZ_4187 3 8 FB10_8
FSM/SHELL1_DSP_SM_2/row_cnt3 6 8 FB10_9 RESET
FSM/SHELL1_DSP_SM_2/row_cnt2 5 8 FB10_10 RESET
FSM/SHELL1_DSP_SM_2/col_cnt0 3 7 FB10_11 RESET
N_PZ_4145 2 6 FB10_12
cntr_cnt<4> 2 6 FB11_6 RESET
cntr_cnt<3> 2 5 FB11_7 RESET
cntr_cnt<2> 2 4 FB11_8 RESET
cntr_cnt<1> 2 3 FB11_9 RESET
cntr_cnt<0> 1 2 FB11_10 RESET
N_PZ_4350 1 2 FB11_11
N_PZ_4285 1 2 FB11_14
cntr_cnt<6> 2 8 FB11_15 RESET
cntr_cnt<5> 2 7 FB11_16 RESET
Signal Total Total Loc Reg Init
Name Pts Inps State
demux_dsp_sel_load<1> 4 11 FB12_6 RESET
demux_dsp_sel_load<0> 4 11 FB12_7 RESET
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 4 8 FB12_8 RESET
N_PZ_4326 4 10 FB12_9
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 5 9 FB12_10 RESET
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 3 8 FB12_11 RESET
demux_dsp_sel_load<3> 4 11 FB13_6 RESET
demux_dsp_sel_load<2> 4 11 FB13_7 RESET
demux_dsp_sel_tri<3> 3 10 FB13_8 RESET
demux_dsp_sel_tri<2> 3 10 FB13_9 RESET
demux_dsp_sel_tri<1> 3 10 FB13_10 RESET
demux_dsp_sel_tri<0> 3 10 FB13_11 RESET
N_PZ_4291 1 2 FB14_3
N_PZ_4354 1 22 FB14_6
N_PZ_4253 2 24 FB14_7
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 1 23 FB14_8
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 1 24 FB14_9
REG_DSIQTIME_0/stored_value<1> 2 2 FB14_10 RESET
REG_DSIQTIME_0/stored_value<0> 2 2 FB14_11 RESET
N_PZ_4324 4 9 FB14_14
REG_DSIQTIME_0/stored_value<3> 2 2 FB14_15 RESET
REG_DSIQTIME_0/stored_value<2> 2 2 FB14_16 RESET
CHIPDEMUX_TRI/_n000117 2 4 FB15_6
CHIPDEMUX_TRI/_n000118 2 3 FB15_7
N_PZ_4371 1 3 FB15_8
DSPDEMUX_LOAD/_n000118 2 3 FB15_9
DSPDEMUX_LOAD/_n000117 2 4 FB15_10
N_PZ_4208 18 17 FB15_11
N_PZ_4458 1 14 FB16_7
chip_sel_tri<7> 2 6 FB16_8 RESET
dsp_sel_tri<0> 2 6 FB16_9 RESET
DSPDEMUX_TRI/_n000117 2 4 FB16_10
DSPDEMUX_TRI/_n000118 2 3 FB16_11
** 10 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
dsp_asm2_l FB10_4 148 I/O I
dsp_are_l FB10_5 147 I/O I
dsp_awe_l FB10_12 146 I/O I
dsp_add<3> FB14_15 120 I/O I
dsp_add<2> FB14_16 119 I/O I
reset FB15_4 96 I/O I
fake_transmit FB15_15 101 I/O I
dsp_add<1> FB16_1 118 I/O I
dsp_add<0> FB16_2 117 I/O I
CLK 181 GCK/I GCK/I
Legend:
Pin No. - ~ - User Assigned
PU - Pull Up
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global clock
O - Output (b) - Buried macrocell
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 29/11
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 3/5
Number of PLA product terms used/remaining: 48/0
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
dsp_data<2> 3 FB1_1 6 I/O I/O
dsp_data<3> 3 FB1_2 7 I/O I/O
dsp_data<4> 2 FB1_3 8 I/O I/O
dsp_data<5> 2 FB1_4 9 I/O I/O
dsp_data<6> 2 FB1_5 10 I/O I/O
(unused) 0 FB1_6 (b)
FSM/SHELL1_DSP_SM_2/col_cnt1 5 FB1_7 (b) (b) CLK
status_reg_data<3> 12 FB1_8 (b) (b) CLK
status_reg_load 13 FB1_9 (b) (b) CLK
status_reg_data<0> 11 FB1_10 (b) (b) CLK
status_reg_data<2> 9 FB1_11 (b) (b) CLK
dsp_data<7> 2 FB1_12 11 I/O I/O
(unused) 0 FB1_13 12 I/O
(unused) 0 FB1_14 13 I/O
(unused) 0 FB1_15 15 I/O
(unused) 0 FB1_16 16 I/O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/col_cnt0 11: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 21: N_PZ_4350
2: FSM/SHELL1_DSP_SM_2/col_cnt1 12: FSM/SHELL1_DSP_SM_2/tochip_command0 22: N_PZ_4398
3: FSM/SHELL1_DSP_SM_2/col_cnt2 13: FSM/SHELL1_DSP_SM_2/tochip_command1 23: N_PZ_4399
4: FSM/SHELL1_DSP_SM_2/col_cnt3 14: N_PZ_4093 24: dsp_sel_tri<0>
5: FSM/SHELL1_DSP_SM_2/col_cnt4 15: N_PZ_4126 25: status_reg_data<0>
6: FSM/SHELL1_DSP_SM_2/col_cnt5 16: N_PZ_4187 26: status_reg_data<2>
7: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 17: N_PZ_4283 27: status_reg_data<3>
8: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 18: N_PZ_4285 28: status_reg_load
9: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 19: N_PZ_4291 29: status_reg_load_out
10: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 20: N_PZ_4299
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dsp_data<2> .......................X.X.X............ 3
dsp_data<3> .......................X..XX............ 3
dsp_data<4> .......................X....X........... 2
dsp_data<5> .......................X....X........... 2
dsp_data<6> .......................X....X........... 2
FSM/SHELL1_DSP_SM_2/col_cnt1
XXXXXXXXXX...X...X.XX................... 14
status_reg_data<3>
XXXXXX.XXXXXXXX...XXXX....X............. 19
status_reg_load XXXXXXXXXXXXX.XX.XXXX......X............ 20
status_reg_data<0>
......XXXXX..X.X.XXXXXX.X............... 14
status_reg_data<2>
......XXXXX....XXXXXXXX..X.............. 14
dsp_data<7> .......................X....X........... 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 35/5
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 48/0
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
dsp_data<1> 3 FB2_1 4 I/O I/O
dsp_data<0> 3 FB2_2 3 I/O I/O
(unused) 0 FB2_3 206 I/O
(unused) 0 FB2_4 205 I/O
(unused) 0 FB2_5 204 I/O
N_PZ_4399 5 FB2_6 (b) (b)
FSM/SHELL1_DSP_SM_2/row_cnt0 4 FB2_7 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/row_cnt1 4 FB2_8 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2
11 FB2_9 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5
11 FB2_10 (b) (b) CLK
status_reg_data<1> 10 FB2_11 (b) (b) CLK
(unused) 0 FB2_12 203 I/O
(unused) 0 FB2_13 202 I/O
FSM/SHELL1_DSP_SM_2/col_cnt2 5 FB2_14 201 I/O (b) CLK
data<0> 2 FB2_15 199 I/O O
data<1> 2 FB2_16 198 I/O O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/col_cnt0 13: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 25: N_PZ_4285
2: FSM/SHELL1_DSP_SM_2/col_cnt1 14: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 26: N_PZ_4291
3: FSM/SHELL1_DSP_SM_2/col_cnt2 15: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 27: N_PZ_4299
4: FSM/SHELL1_DSP_SM_2/col_cnt3 16: FSM/SHELL1_DSP_SM_2/tochip_command0 28: N_PZ_4350
5: FSM/SHELL1_DSP_SM_2/col_cnt4 17: FSM/SHELL1_DSP_SM_2/tochip_command1 29: N_PZ_4399
6: FSM/SHELL1_DSP_SM_2/col_cnt5 18: N_PZ_4093 30: data<8>
7: FSM/SHELL1_DSP_SM_2/row_cnt0 19: N_PZ_4126 31: data<9>
8: FSM/SHELL1_DSP_SM_2/row_cnt1 20: N_PZ_4127 32: dsp_sel_tri<0>
9: FSM/SHELL1_DSP_SM_2/row_cnt2 21: N_PZ_4145 33: status_reg_data<0>
10: FSM/SHELL1_DSP_SM_2/row_cnt3 22: N_PZ_4187 34: status_reg_data<1>
11: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 23: N_PZ_4208 35: status_reg_load
12: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 24: N_PZ_4283
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dsp_data<1> ...............................X.XX..... 3
dsp_data<0> ...............................XX.X..... 3
N_PZ_4399 XXXXXX....XXXXXXX..........X............ 14
FSM/SHELL1_DSP_SM_2/row_cnt0
XXXXXXX...XXXXX.........X............... 13
FSM/SHELL1_DSP_SM_2/row_cnt1
XXXXXXXX..XXXXX.........X............... 14
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2
XXXXXXXXXXXXXXXXXXX...X....X............ 21
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5
XXXXXX....XXXXXX.XXX.X...XXX............ 19
status_reg_data<1>
..........XXXXX...X.....XXX.X....X...... 11
FSM/SHELL1_DSP_SM_2/col_cnt2
XXXXXX....XXXXX.....X..XX............... 14
data<0> .............................X.......... 1
data<1> ..............................X......... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 36/4
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 48/0
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
(unused) 0 FB3_1 17 I/O
PRE 5 FB3_2 18 I/O O CLK
SAN 1 FB3_3 19 I/O O
pre_sleep 2 FB3_4 20 I/O O CLK
imp_slp 0 FB3_5 21 I/O O
(unused) 0 FB3_6 (b)
(unused) 0 FB3_7 (b)
(unused) 0 FB3_8 (b)
(unused) 0 FB3_9 (b)
(unused) 0 FB3_10 (b)
N_PZ_4299 1 FB3_11 (b) (b)
post_sleep 1 FB3_12 22 I/O O
row_pulse 1 FB3_13 24 I/O O
row_clk 11 FB3_14 25 I/O O CLK
col_clk 11 FB3_15 26 I/O O CLK
sel_clk 21 FB3_16 27 I/O O CLK
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/col_cnt0 13: FSM/SHELL1_DSP_SM_2/sel_cnt2 25: N_PZ_4299
2: FSM/SHELL1_DSP_SM_2/col_cnt1 14: FSM/SHELL1_DSP_SM_2/sel_cnt3 26: N_PZ_4350
3: FSM/SHELL1_DSP_SM_2/col_cnt2 15: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 27: N_PZ_4398
4: FSM/SHELL1_DSP_SM_2/col_cnt3 16: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 28: N_PZ_4401
5: FSM/SHELL1_DSP_SM_2/col_cnt4 17: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 29: PRE
6: FSM/SHELL1_DSP_SM_2/col_cnt5 18: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 30: SAN_BUFR
7: FSM/SHELL1_DSP_SM_2/row_cnt0 19: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 31: col_clk
8: FSM/SHELL1_DSP_SM_2/row_cnt1 20: N_PZ_4093 32: post_sleep_BUFR
9: FSM/SHELL1_DSP_SM_2/row_cnt2 21: N_PZ_4126 33: pre_sleep
10: FSM/SHELL1_DSP_SM_2/row_cnt3 22: N_PZ_4127 34: row_clk
11: FSM/SHELL1_DSP_SM_2/sel_cnt0 23: N_PZ_4187 35: row_pulse_BUFR
12: FSM/SHELL1_DSP_SM_2/sel_cnt1 24: N_PZ_4285 36: sel_clk
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
PRE ..............XX.X....XXX..XX........... 8
SAN .............................X.......... 1
pre_sleep .....................X..........X....... 2
imp_slp ........................................ 0
N_PZ_4299 ..........XXXX.......................... 4
post_sleep ...............................X........ 1
row_pulse ..................................X..... 1
row_clk XXXXXX........XXXXXXX..XXX.......X...... 17
col_clk XXXXXX....XXXXXXXXXX..XXXX....X......... 21
sel_clk XXXXXXXXXXXXXXXXXXXXXX.XXXX........X.... 27
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 48/0
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
data<2> 3 FB4_1 197 I/O O
data<3> 3 FB4_2 196 I/O O
data<4> 2 FB4_3 195 I/O O
data<5> 3 FB4_4 194 I/O O
data<6> 3 FB4_5 193 I/O O
cntr_cnt<7> 2 FB4_6 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4
10 FB4_7 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/cntr_rst 14 FB4_8 (b) (b) CLK
demux_chip_sel_tri<2> 4 FB4_9 (b) (b) CLK
demux_chip_sel_tri<1> 4 FB4_10 (b) (b) CLK
demux_chip_sel_tri<0> 4 FB4_11 (b) (b) CLK
data<7> 3 FB4_12 192 I/O O
(unused) 0 FB4_13 190 I/O
demux_chip_sel_tri<3> 3 FB4_14 189 TDO/I/O (b) CLK
(unused) 0 FB4_15 188 I/O
FSM/SHELL1_DSP_SM_2/todsp_command0
3 FB4_16 187 I/O (b) CLK
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/cntr_rst 14: N_PZ_4093 27: cntr_cnt<6>
2: FSM/SHELL1_DSP_SM_2/row_cnt0 15: N_PZ_4126 28: cntr_cnt<7>
3: FSM/SHELL1_DSP_SM_2/row_cnt1 16: N_PZ_4127 29: cntr_sel
4: FSM/SHELL1_DSP_SM_2/row_cnt2 17: N_PZ_4208 30: cntr_set_value<2>
5: FSM/SHELL1_DSP_SM_2/row_cnt3 18: N_PZ_4285 31: cntr_set_value<3>
6: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 19: N_PZ_4350 32: cntr_set_value<5>
7: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 20: N_PZ_4398 33: cntr_set_value<6>
8: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 21: cntr_cnt<0> 34: cntr_set_value<7>
9: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 22: cntr_cnt<1> 35: demux_chip_sel_tri<0>
10: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 23: cntr_cnt<2> 36: demux_chip_sel_tri<1>
11: FSM/SHELL1_DSP_SM_2/tochip_command0 24: cntr_cnt<3> 37: demux_chip_sel_tri<2>
12: FSM/SHELL1_DSP_SM_2/tochip_command1 25: cntr_cnt<4> 38: demux_chip_sel_tri<3>
13: FSM/SHELL1_DSP_SM_2/todsp_command0 26: cntr_cnt<5>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
data<2> ......................X.....XX.......... 3
data<3> .......................X....X.X......... 3
data<4> ........................X...X........... 2
data<5> .........................X..X..X........ 3
data<6> ..........................X.X...X....... 3
cntr_cnt<7> X...................XXXXXXXX............ 9
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4
.....XXXXX...XX..XXXXXXXXXXX............ 18
FSM/SHELL1_DSP_SM_2/cntr_rst
XXXXXXXXXXXX..XX.XXXXXXXXXXX............ 25
demux_chip_sel_tri<2>
......X.XX.....XXXX.XXXXXXXX........X... 16
demux_chip_sel_tri<1>
......X.XX.....XXXX.XXXXXXXX.......X.... 16
demux_chip_sel_tri<0>
......X.XX.....XXXX.XXXXXXXX......X..... 16
data<7> ...........................XX....X...... 3
demux_chip_sel_tri<3>
......X.XX.......XX.XXXXXXXX.........X.. 14
FSM/SHELL1_DSP_SM_2/todsp_command0
.....XXXXXXXX....X...................... 9
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 34/6
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 47/1
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
col_pulse 3 FB5_1 28 I/O O CLK
sel_pulse 9 FB5_2 29 I/O O CLK
cntr_set_value<3> 7 FB5_3 30 TCK/I/O (b) CLK
wr_clk_en 0 FB5_4 31 I/O O
comp_sleep 3 FB5_5 33 I/O O CLK
FSM/SHELL1_DSP_SM_2/sel_cnt3 7 FB5_6 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sel_cnt2 7 FB5_7 (b) (b) CLK
N_PZ_4460 1 FB5_8 (b) (b)
cntr_tri 9 FB5_9 (b) (b) CLK
N_PZ_4112 4 FB5_10 (b) (b)
FSM/SHELL1_DSP_SM_2/ramp_cnt0 7 FB5_11 (b) (b) CLK
SH_samp_0 3 FB5_12 34 I/O O CLK
SH_samp_1 0 FB5_13 35 I/O O
SH_samp_2 0 FB5_14 36 I/O O
SH_samp_3 0 FB5_15 37 I/O O
VREG_EN_l 0 FB5_16 38 I/O O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/ramp_cnt0 13: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 24: N_PZ_4299
2: FSM/SHELL1_DSP_SM_2/ramp_cnt1 14: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 25: N_PZ_4350
3: FSM/SHELL1_DSP_SM_2/ramp_cnt2 15: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 26: N_PZ_4398
4: FSM/SHELL1_DSP_SM_2/ramp_cnt3 16: N_PZ_4093 27: N_PZ_4401
5: FSM/SHELL1_DSP_SM_2/ramp_cnt4 17: N_PZ_4127 28: N_PZ_4460
6: FSM/SHELL1_DSP_SM_2/ramp_cnt5 18: N_PZ_4187 29: SH_samp_0
7: FSM/SHELL1_DSP_SM_2/ramp_cnt6 19: N_PZ_4190 30: cntr_set_value<3>
8: FSM/SHELL1_DSP_SM_2/sel_cnt1 20: N_PZ_4192 31: cntr_tri
9: FSM/SHELL1_DSP_SM_2/sel_cnt2 21: N_PZ_4208 32: col_pulse
10: FSM/SHELL1_DSP_SM_2/sel_cnt3 22: N_PZ_4285 33: comp_sleep
11: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 23: N_PZ_4291 34: sel_pulse
12: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
col_pulse ..........XXXXX......X.........X........ 7
sel_pulse XXXXXXX...XXXXX.....XXXXXX.......X...... 19
cntr_set_value<3>
XXXXXXX...XX.XX......XX.XX...X.......... 16
wr_clk_en ........................................ 0
comp_sleep ...........X.XX.X.....X.X.......X....... 7
FSM/SHELL1_DSP_SM_2/sel_cnt3
.......XXXXXXXXX..X.....X............... 11
FSM/SHELL1_DSP_SM_2/sel_cnt2
.......XX.XXXXXX..X....XX............... 11
N_PZ_4460 XXXXXXX...X.X........................... 9
cntr_tri ..........XXXXX.XX....XXXXXX..X......... 14
N_PZ_4112 XXXXXXX.....X.X......X..XX.............. 12
FSM/SHELL1_DSP_SM_2/ramp_cnt0
.XXXXXX.....XXX....X.XX.XX.............. 14
SH_samp_0 ...........X.XX.X...X...X...X........... 7
SH_samp_1 ........................................ 0
SH_samp_2 ........................................ 0
SH_samp_3 ........................................ 0
VREG_EN_l ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 15/25
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 16/32
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
chip_sel<12> 0 FB6_1 78 I/O O
data<21> 2 FB6_2 77 I/O I/O
data<22> 2 FB6_3 76 I/O I/O
data<23> 2 FB6_4 73 I/O I/O
data<24> 2 FB6_5 71 I/O I/O
FSM/SHELL1_DSP_SM_2/ramp_cnt6 2 FB6_6 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramp_cnt5 2 FB6_7 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramp_cnt4 2 FB6_8 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramp_cnt3 2 FB6_9 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramp_cnt2 2 FB6_10 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramp_cnt1 2 FB6_11 (b) (b) CLK
data<25> 2 FB6_12 70 I/O I/O
data<26> 2 FB6_13 69 I/O I/O
data<27> 2 FB6_14 68 I/O I/O
data<28> 2 FB6_15 67 I/O I/O
data<29> 2 FB6_16 66 I/O I/O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/ramp_cnt1 6: N_PZ_4192 11: data<5>
2: FSM/SHELL1_DSP_SM_2/ramp_cnt2 7: cntr_tri 12: data<6>
3: FSM/SHELL1_DSP_SM_2/ramp_cnt3 8: data<2> 13: data<7>
4: FSM/SHELL1_DSP_SM_2/ramp_cnt4 9: data<3> 14: data<8>
5: FSM/SHELL1_DSP_SM_2/ramp_cnt5 10: data<4> 15: data<9>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
chip_sel<12> ........................................ 0
data<21> ......X...X............................. 2
data<22> ......X....X............................ 2
data<23> ......X.....X........................... 2
data<24> ......X......X.......................... 2
FSM/SHELL1_DSP_SM_2/ramp_cnt6
XXXXXX.................................. 6
FSM/SHELL1_DSP_SM_2/ramp_cnt5
XXXX.X.................................. 5
FSM/SHELL1_DSP_SM_2/ramp_cnt4
XXX..X.................................. 4
FSM/SHELL1_DSP_SM_2/ramp_cnt3
XX...X.................................. 3
FSM/SHELL1_DSP_SM_2/ramp_cnt2
X....X.................................. 2
FSM/SHELL1_DSP_SM_2/ramp_cnt1
.....X.................................. 1
data<25> ......X.......X......................... 2
data<26> ......XX................................ 2
data<27> ......X.X............................... 2
data<28> ......X..X.............................. 2
data<29> ......X...X............................. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB7 ***********************************
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 48/0
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
(unused) 0 FB7_1 39 I/O
(unused) 0 FB7_2 40 I/O
(unused) 0 FB7_3 42 I/O
(unused) 0 FB7_4 43 I/O
(unused) 0 FB7_5 44 I/O
FSM/SHELL1_DSP_SM_2/sel_cnt0 6 FB7_6 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/col_cnt5 8 FB7_7 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/col_cnt4 7 FB7_8 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/col_cnt3 6 FB7_9 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3
10 FB7_10 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1
12 FB7_11 (b) (b) CLK
(unused) 0 FB7_12 45 I/O
(unused) 0 FB7_13 46 I/O
N_PZ_4093 2 FB7_14 47 I/O (b)
row_pulse_BUFR 5 FB7_15 48 I/O (b)
post_sleep_BUFR 6 FB7_16 49 I/O (b)
Signals Used by Logic in Function Block
1: CLK 14: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 27: N_PZ_4398
2: FSM/SHELL1_DSP_SM_2/col_cnt0 15: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 28: N_PZ_4460
3: FSM/SHELL1_DSP_SM_2/col_cnt1 16: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 29: cntr_cnt<0>
4: FSM/SHELL1_DSP_SM_2/col_cnt2 17: FSM/SHELL1_DSP_SM_2/tochip_command0 30: cntr_cnt<1>
5: FSM/SHELL1_DSP_SM_2/col_cnt3 18: FSM/SHELL1_DSP_SM_2/tochip_command1 31: cntr_cnt<2>
6: FSM/SHELL1_DSP_SM_2/col_cnt4 19: N_PZ_4093 32: cntr_cnt<3>
7: FSM/SHELL1_DSP_SM_2/col_cnt5 20: N_PZ_4145 33: cntr_cnt<4>
8: FSM/SHELL1_DSP_SM_2/sel_cnt0 21: N_PZ_4190 34: cntr_cnt<5>
9: FSM/SHELL1_DSP_SM_2/sel_cnt1 22: N_PZ_4208 35: cntr_cnt<6>
10: FSM/SHELL1_DSP_SM_2/sel_cnt2 23: N_PZ_4283 36: cntr_cnt<7>
11: FSM/SHELL1_DSP_SM_2/sel_cnt3 24: N_PZ_4285 37: post_sleep_BUFR
12: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 25: N_PZ_4291 38: row_pulse_BUFR
13: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 26: N_PZ_4350
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
FSM/SHELL1_DSP_SM_2/sel_cnt0
.......XXXXXXXXXXXX.X....X.............. 14
FSM/SHELL1_DSP_SM_2/col_cnt5
.XXXXXX....XXXXX...X..XX................ 14
FSM/SHELL1_DSP_SM_2/col_cnt4
.XXXXXX....XXXXX...X..XX................ 14
FSM/SHELL1_DSP_SM_2/col_cnt3
.XXXXXX....XXXXX...X..XX................ 14
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3
.XXXXXX....XXXXX.......XXX.XXXXXXXXX.... 23
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1
.XXXXXXXXXXXXXXXXX...X.X.X..XXXXXXXX.... 28
N_PZ_4093 ............XXXX........................ 4
row_pulse_BUFR XXXXXXX....XXXXX.......X.............X.. 14
post_sleep_BUFR X...........X.XX.......XX.X.XXXXXXXXX... 16
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 22/18
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 21/27
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
data<30> 2 FB8_1 65 I/O I/O
data<31> 2 FB8_2 64 I/O I/O
rb_pd_l 0 FB8_3 62 I/O O
dac_clk 1 FB8_4 61 I/O O
dac_cs_l 0 FB8_5 60 I/O O
cntr_set_value<6> 4 FB8_6 (b) (b) CLK
cntr_set_value<5> 3 FB8_7 (b) (b) CLK
cntr_set_value<2> 3 FB8_8 (b) (b) CLK
cntr_set_value<0> 3 FB8_9 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramps0 3 FB8_10 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/ramps1 3 FB8_11 (b) (b) CLK
dac_pd 0 FB8_12 59 I/O O
dac_en 2 FB8_13 58 I/O O CLK
cntr_8 3 FB8_14 57 I/O O CLK
cntr_9 3 FB8_15 56 I/O O CLK
cntr_set_value<7> 3 FB8_16 55 I/O (b) CLK
Signals Used by Logic in Function Block
1: CLK 9: N_PZ_4291 16: cntr_set_value<5>
2: FSM/SHELL1_DSP_SM_2/ramps0 10: N_PZ_4350 17: cntr_set_value<6>
3: FSM/SHELL1_DSP_SM_2/ramps1 11: N_PZ_4460 18: cntr_set_value<7>
4: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 12: cntr_8 19: dac_en
5: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 13: cntr_9 20: data<6>
6: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 14: cntr_set_value<0> 21: data<7>
7: N_PZ_4112 15: cntr_set_value<2> 22: reset
8: N_PZ_4127
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
data<30> ...................X.................... 1
data<31> ....................X................... 1
rb_pd_l ........................................ 0
dac_clk X....................................... 1
dac_cs_l ........................................ 0
cntr_set_value<6>
...XXXX.XX......X....X.................. 8
cntr_set_value<5>
...XXXX..X.....X.....X.................. 7
cntr_set_value<2>
...XXXX..X....X......X.................. 7
cntr_set_value<0>
...XXXX..X...X.......X.................. 7
FSM/SHELL1_DSP_SM_2/ramps0
.X..XX.X.X...........X.................. 6
FSM/SHELL1_DSP_SM_2/ramps1
.XXXXX.X.X...........X.................. 8
dac_pd ........................................ 0
dac_en .......X..........X..X.................. 3
cntr_8 ...XXX.X..XX.........X.................. 7
cntr_9 ...XXX.X..X.X........X.................. 7
cntr_set_value<7>
...XXXX.XX.......X...X.................. 8
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB9 ***********************************
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 39/9
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
N_PZ_4387 2 FB9_1 153 I/O (b)
N_PZ_4401 5 FB9_2 154 I/O (b)
SAN_BUFR 10 FB9_3 159 I/O (b)
data<15> 2 FB9_4 160 I/O I/O
data<14> 2 FB9_5 161 I/O I/O
FSM/SHELL1_DSP_SM_2/sel_cnt1 5 FB9_6 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/todsp_command1
3 FB9_7 (b) (b) CLK
N_PZ_4192 2 FB9_8 (b) (b)
sample_reg_load 4 FB9_9 (b) (b) CLK
cntr_set_value<1> 4 FB9_10 (b) (b) CLK
cntr_sel 2 FB9_11 (b) (b) CLK
data<13> 2 FB9_12 162 I/O I/O
data<12> 2 FB9_13 163 I/O I/O
data<11> 2 FB9_14 164 I/O I/O
data<10> 2 FB9_15 166 I/O I/O
data<9> 3 FB9_16 167 I/O I/O
Signals Used by Logic in Function Block
1: CLK 14: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 27: N_PZ_4398
2: FSM/SHELL1_DSP_SM_2/col_cnt0 15: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 28: SAN_BUFR
3: FSM/SHELL1_DSP_SM_2/col_cnt1 16: FSM/SHELL1_DSP_SM_2/tochip_command0 29: cntr_cnt<1>
4: FSM/SHELL1_DSP_SM_2/col_cnt2 17: FSM/SHELL1_DSP_SM_2/tochip_command1 30: cntr_sel
5: FSM/SHELL1_DSP_SM_2/col_cnt3 18: FSM/SHELL1_DSP_SM_2/todsp_command1 31: cntr_set_value<1>
6: FSM/SHELL1_DSP_SM_2/col_cnt4 19: N_PZ_4093 32: data<2>
7: FSM/SHELL1_DSP_SM_2/col_cnt5 20: N_PZ_4112 33: data<3>
8: FSM/SHELL1_DSP_SM_2/ramp_cnt0 21: N_PZ_4187 34: data<4>
9: FSM/SHELL1_DSP_SM_2/row_cnt1 22: N_PZ_4190 35: data<5>
10: FSM/SHELL1_DSP_SM_2/sel_cnt1 23: N_PZ_4283 36: data<6>
11: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 24: N_PZ_4285 37: data<7>
12: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 25: N_PZ_4291 38: sample_reg_load
13: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 26: N_PZ_4350
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
N_PZ_4387 .XXXXXX.X.XXXXX......................... 12
N_PZ_4401 .XXXXXX...XXXXX.....X..X................ 13
SAN_BUFR XXXXXXX...X.XXX...X.X.XX.XXX............ 18
data<15> ....................................X... 1
data<14> ...................................X.... 1
FSM/SHELL1_DSP_SM_2/sel_cnt1
.........XXXXXX...X..X...X.............. 9
FSM/SHELL1_DSP_SM_2/todsp_command1
..........XXXXXXXX.....X................ 9
N_PZ_4192 .......X...X.XX........XXX.............. 7
sample_reg_load ...........X.XX........XXX...........X.. 7
cntr_set_value<1>
.............X.....X....XXX...X......... 6
cntr_sel ...................X.........X.......... 2
data<13> ..................................X..... 1
data<12> .................................X...... 1
data<11> ................................X....... 1
data<10> ...............................X........ 1
data<9> ............................XXX......... 3
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB10 ***********************************
Number of function block inputs used/remaining: 37/3
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 40/8
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
FSM/SHELL1_DSP_SM_2/tochip_command1
5 FB10_1 151 I/O (b) CLK
FSM/SHELL1_DSP_SM_2/tochip_command0
5 FB10_2 150 I/O (b) CLK
N_PZ_4127 2 FB10_3 149 I/O (b)
N_PZ_4398 2 FB10_4 148 I/O I
N_PZ_4283 2 FB10_5 147 I/O I
N_PZ_4190 2 FB10_6 (b) (b)
N_PZ_4126 4 FB10_7 (b) (b)
N_PZ_4187 3 FB10_8 (b) (b)
FSM/SHELL1_DSP_SM_2/row_cnt3 6 FB10_9 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/row_cnt2 5 FB10_10 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/col_cnt0 3 FB10_11 (b) (b) CLK
N_PZ_4145 2 FB10_12 146 I/O I
dsp_data<8> 2 FB10_13 145 I/O I/O
dsp_data<9> 2 FB10_14 144 I/O I/O
dsp_data<10> 2 FB10_15 142 I/O I/O
dsp_data<11> 2 FB10_16 141 I/O I/O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/col_cnt0 14: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 26: N_PZ_4354
2: FSM/SHELL1_DSP_SM_2/col_cnt1 15: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 27: N_PZ_4371
3: FSM/SHELL1_DSP_SM_2/row_cnt0 16: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 28: N_PZ_4387
4: FSM/SHELL1_DSP_SM_2/row_cnt1 17: FSM/SHELL1_DSP_SM_2/tochip_command0 29: data<10>.PIN
5: FSM/SHELL1_DSP_SM_2/row_cnt2 18: FSM/SHELL1_DSP_SM_2/tochip_command1 30: data<11>.PIN
6: FSM/SHELL1_DSP_SM_2/row_cnt3 19: N_PZ_4093 31: data<8>.PIN
7: FSM/SHELL1_DSP_SM_2/sel_cnt0 20: N_PZ_4126 32: data<9>.PIN
8: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 21: N_PZ_4208 33: dsp_are_l
9: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 22: N_PZ_4283 34: dsp_asm2_l
10: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 23: N_PZ_4285 35: dsp_awe_l
11: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 24: N_PZ_4299 36: dsp_data<0>.PIN
12: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 25: N_PZ_4350 37: fake_transmit
13: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
FSM/SHELL1_DSP_SM_2/tochip_command1
............XXXX.X.......XX.....XXXXX... 12
FSM/SHELL1_DSP_SM_2/tochip_command0
............XXX.X........X......XXX.X... 9
N_PZ_4127 ........X.XX........X...X............... 5
N_PZ_4398 ........X.XX............X............... 4
N_PZ_4283 .......X.X.X...........XX............... 5
N_PZ_4190 ......XXXXXX....XX...................... 8
N_PZ_4126 ..XXXX.XXX.X..........X................. 9
N_PZ_4187 ..XXXX..XX.X.......X.................... 8
FSM/SHELL1_DSP_SM_2/row_cnt3
..X.XX...XXX.......X.......X............ 8
FSM/SHELL1_DSP_SM_2/row_cnt2
..X.X..XXXX.......X........X............ 8
FSM/SHELL1_DSP_SM_2/col_cnt0
X......XXXXX.........X.................. 7
N_PZ_4145 XX.....X.X........X....X................ 6
dsp_data<8> ..............................X......... 1
dsp_data<9> ...............................X........ 1
dsp_data<10> ............................X........... 1
dsp_data<11> .............................X.......... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB11 ***********************************
Number of function block inputs used/remaining: 36/4
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 33/15
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
data<8> 3 FB11_1 168 I/O I/O
chip_sel<5> 0 FB11_2 169 I/O O
chip_sel<6> 0 FB11_3 170 I/O O
chip_sel<3> 0 FB11_4 171 I/O O
chip_sel<4> 0 FB11_5 172 I/O O
cntr_cnt<4> 2 FB11_6 (b) (b) CLK
cntr_cnt<3> 2 FB11_7 (b) (b) CLK
cntr_cnt<2> 2 FB11_8 (b) (b) CLK
cntr_cnt<1> 2 FB11_9 (b) (b) CLK
cntr_cnt<0> 1 FB11_10 (b) (b) CLK
N_PZ_4350 1 FB11_11 (b) (b)
chip_sel<1> 17 FB11_12 173 I/O O CLK
chip_sel<2> 0 FB11_13 175 I/O O
N_PZ_4285 1 FB11_14 176 TDI/I/O (b)
cntr_cnt<6> 2 FB11_15 177 I/O (b) CLK
cntr_cnt<5> 2 FB11_16 178 I/O (b) CLK
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/cntr_rst 13: FSM/SHELL1_DSP_SM_2/sel_cnt1 25: N_PZ_4285
2: FSM/SHELL1_DSP_SM_2/col_cnt0 14: FSM/SHELL1_DSP_SM_2/sel_cnt2 26: N_PZ_4350
3: FSM/SHELL1_DSP_SM_2/col_cnt1 15: FSM/SHELL1_DSP_SM_2/sel_cnt3 27: chip_sel<1>
4: FSM/SHELL1_DSP_SM_2/col_cnt2 16: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 28: cntr_cnt<0>
5: FSM/SHELL1_DSP_SM_2/col_cnt3 17: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 29: cntr_cnt<1>
6: FSM/SHELL1_DSP_SM_2/col_cnt4 18: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 30: cntr_cnt<2>
7: FSM/SHELL1_DSP_SM_2/col_cnt5 19: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 31: cntr_cnt<3>
8: FSM/SHELL1_DSP_SM_2/row_cnt0 20: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 32: cntr_cnt<4>
9: FSM/SHELL1_DSP_SM_2/row_cnt1 21: FSM/SHELL1_DSP_SM_2/tochip_command0 33: cntr_cnt<5>
10: FSM/SHELL1_DSP_SM_2/row_cnt2 22: FSM/SHELL1_DSP_SM_2/tochip_command1 34: cntr_cnt<6>
11: FSM/SHELL1_DSP_SM_2/row_cnt3 23: N_PZ_4093 35: cntr_sel
12: FSM/SHELL1_DSP_SM_2/sel_cnt0 24: N_PZ_4127 36: cntr_set_value<0>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
data<8> ...........................X......XX.... 3
chip_sel<5> ........................................ 0
chip_sel<6> ........................................ 0
chip_sel<3> ........................................ 0
chip_sel<4> ........................................ 0
cntr_cnt<4> X..........................XXXXX........ 6
cntr_cnt<3> X..........................XXXX......... 5
cntr_cnt<2> X..........................XXX.......... 4
cntr_cnt<1> X..........................XX........... 3
cntr_cnt<0> X..........................X............ 2
N_PZ_4350 ...............X.X...................... 2
chip_sel<1> .XXXXXXXXXXXXXXXXXXXXXXXXXX............. 26
chip_sel<2> ........................................ 0
N_PZ_4285 ...............X.X...................... 2
cntr_cnt<6> X..........................XXXXXXX...... 8
cntr_cnt<5> X..........................XXXXXX....... 7
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB12 ***********************************
Number of function block inputs used/remaining: 27/13
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 23/25
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
dsp_data<12> 2 FB12_1 140 I/O I/O
dsp_data<13> 2 FB12_2 139 I/O I/O
dsp_data<14> 2 FB12_3 138 I/O I/O
dsp_data<15> 2 FB12_4 137 I/O I/O
dsp_data<16> 2 FB12_5 136 I/O I/O
demux_dsp_sel_load<1> 4 FB12_6 (b) (b) CLK
demux_dsp_sel_load<0> 4 FB12_7 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1
4 FB12_8 (b) (b) CLK
N_PZ_4326 4 FB12_9 (b) (b)
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3
5 FB12_10 (b) (b) CLK
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2
3 FB12_11 (b) (b) CLK
dsp_data<17> 2 FB12_12 135 I/O I/O
dsp_data<18> 2 FB12_13 133 I/O I/O
dsp_data<19> 2 FB12_14 132 I/O I/O
dsp_data<20> 2 FB12_15 131 I/O I/O
dsp_data<21> 2 FB12_16 130 I/O I/O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 10: data<12>.PIN 19: data<21>.PIN
2: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 11: data<13>.PIN 20: demux_dsp_sel_load<0>
3: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 12: data<14>.PIN 21: demux_dsp_sel_load<1>
4: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 13: data<15>.PIN 22: dsp_add<0>
5: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 14: data<16>.PIN 23: dsp_add<1>
6: N_PZ_4253 15: data<17>.PIN 24: dsp_are_l
7: N_PZ_4326 16: data<18>.PIN 25: dsp_asm2_l
8: N_PZ_4354 17: data<19>.PIN 26: dsp_awe_l
9: N_PZ_4371 18: data<20>.PIN 27: fake_transmit
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dsp_data<12> .........X.............................. 1
dsp_data<13> ..........X............................. 1
dsp_data<14> ...........X............................ 1
dsp_data<15> ............X........................... 1
dsp_data<16> .............X.......................... 1
demux_dsp_sel_load<1>
XX.X..XX............X.XXXXX............. 11
demux_dsp_sel_load<0>
XX.X..XX...........X.X.XXXX............. 11
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1
XX.X...X...............XXXX............. 8
N_PZ_4326 XX.XX..XX..............XXXX............. 10
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3
XX.XX...X..............XXXX............. 9
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2
XXXX.X..X...............X.X............. 8
dsp_data<17> ..............X......................... 1
dsp_data<18> ...............X........................ 1
dsp_data<19> ................X....................... 1
dsp_data<20> .................X...................... 1
dsp_data<21> ..................X..................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB13 ***********************************
Number of function block inputs used/remaining: 26/14
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 0/8
Number of PLA product terms used/remaining: 18/30
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
chip_sel<11> 0 FB13_1 79 I/O O
chip_sel<10> 0 FB13_2 80 I/O O
chip_sel<9> 0 FB13_3 81 I/O O
chip_sel<8> 0 FB13_4 84 I/O O
chip_sel<7> 0 FB13_5 86 I/O O
demux_dsp_sel_load<3> 4 FB13_6 (b) (b) CLK
demux_dsp_sel_load<2> 4 FB13_7 (b) (b) CLK
demux_dsp_sel_tri<3> 3 FB13_8 (b) (b) CLK
demux_dsp_sel_tri<2> 3 FB13_9 (b) (b) CLK
demux_dsp_sel_tri<1> 3 FB13_10 (b) (b) CLK
demux_dsp_sel_tri<0> 3 FB13_11 (b) (b) CLK
data<20> 2 FB13_12 87 I/O I/O
data<19> 2 FB13_13 88 I/O I/O
data<18> 2 FB13_14 89 I/O I/O
data<17> 2 FB13_15 90 I/O I/O
data<16> 2 FB13_16 91 I/O I/O
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 10: data<4> 19: dsp_add<0>
2: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 11: data<8> 20: dsp_add<1>
3: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 12: data<9> 21: dsp_add<2>
4: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 13: demux_dsp_sel_load<2> 22: dsp_add<3>
5: N_PZ_4324 14: demux_dsp_sel_load<3> 23: dsp_are_l
6: N_PZ_4326 15: demux_dsp_sel_tri<0> 24: dsp_asm2_l
7: N_PZ_4354 16: demux_dsp_sel_tri<1> 25: dsp_awe_l
8: data<2> 17: demux_dsp_sel_tri<2> 26: fake_transmit
9: data<3> 18: demux_dsp_sel_tri<3>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
chip_sel<11> ........................................ 0
chip_sel<10> ........................................ 0
chip_sel<9> ........................................ 0
chip_sel<8> ........................................ 0
chip_sel<7> ........................................ 0
demux_dsp_sel_load<3>
XXX..XX......X.......XXXXX.............. 11
demux_dsp_sel_load<2>
XXX..XX.....X.......X.XXXX.............. 11
demux_dsp_sel_tri<3>
XXXXX............X...XXX.X.............. 10
demux_dsp_sel_tri<2>
XXXXX...........X...X.XX.X.............. 10
demux_dsp_sel_tri<1>
XXXXX..........X...X..XX.X.............. 10
demux_dsp_sel_tri<0>
XXXXX.........X...X...XX.X.............. 10
data<20> .........X.............................. 1
data<19> ........X............................... 1
data<18> .......X................................ 1
data<17> ...........X............................ 1
data<16> ..........X............................. 1
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB14 ***********************************
Number of function block inputs used/remaining: 38/2
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 17/31
Number of function block global clocks used/remaining: 0/2
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
dsp_data<22> 2 FB14_1 129 I/O I/O
dsp_data<23> 2 FB14_2 128 I/O I/O
N_PZ_4291 1 FB14_3 127 TMS/I/O (b)
dsp_data<24> 2 FB14_4 126 I/O I/O
(unused) 0 FB14_5 124 I/O
N_PZ_4354 1 FB14_6 (b) (b)
N_PZ_4253 2 FB14_7 (b) (b)
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51
1 FB14_8 (b) (b)
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93
1 FB14_9 (b) (b)
REG_DSIQTIME_0/stored_value<1>
2 FB14_10 (b) (b)
REG_DSIQTIME_0/stored_value<0>
2 FB14_11 (b) (b)
(unused) 0 FB14_12 123 I/O
(unused) 0 FB14_13 122 I/O
N_PZ_4324 4 FB14_14 121 I/O (b)
REG_DSIQTIME_0/stored_value<3>
2 FB14_15 120 I/O I
REG_DSIQTIME_0/stored_value<2>
2 FB14_16 119 I/O I
Signals Used by Logic in Function Block
1: FSM/SHELL1_DSP_SM_2/ramps0 14: dsp_add<2> 27: dsp_data<2>.PIN
2: FSM/SHELL1_DSP_SM_2/ramps1 15: dsp_add<3> 28: dsp_data<30>.PIN
3: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 16: dsp_are_l 29: dsp_data<31>.PIN
4: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 17: dsp_asm2_l 30: dsp_data<3>.PIN
5: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 18: dsp_awe_l 31: dsp_data<4>.PIN
6: N_PZ_4354 19: dsp_data<0>.PIN 32: dsp_data<5>.PIN
7: N_PZ_4371 20: dsp_data<1>.PIN 33: dsp_data<6>.PIN
8: N_PZ_4458 21: dsp_data<24>.PIN 34: dsp_data<7>.PIN
9: data<22>.PIN 22: dsp_data<25>.PIN 35: dsp_data<8>.PIN
10: data<23>.PIN 23: dsp_data<26>.PIN 36: dsp_data<9>.PIN
11: data<24>.PIN 24: dsp_data<27>.PIN 37: fake_transmit
12: dsp_add<0> 25: dsp_data<28>.PIN 38: status_reg_load_out
13: dsp_add<1> 26: dsp_data<29>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dsp_data<22> ........X............................... 1
dsp_data<23> .........X.............................. 1
N_PZ_4291 XX...................................... 2
dsp_data<24> ..........X............................. 1
N_PZ_4354 .......X...XXXX....XXXXXXXXXXXXXXXXX.... 22
N_PZ_4253 .......X...XXXXX.X.XXXXXXXXXXXXXXXXX.... 24
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51
.......X...XXXX..X.XXXXXXXXXXXXXXXXX.... 23
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93
.......X...XXXX..XXXXXXXXXXXXXXXXXXX.... 24
REG_DSIQTIME_0/stored_value<1>
...................X.................X.. 2
REG_DSIQTIME_0/stored_value<0>
..................X..................X.. 2
N_PZ_4324 ..XXXXX........XXX..................X... 9
REG_DSIQTIME_0/stored_value<3>
.............................X.......X.. 2
REG_DSIQTIME_0/stored_value<2>
..........................X..........X.. 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB15 ***********************************
Number of function block inputs used/remaining: 37/3
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 1/7
Number of PLA product terms used/remaining: 31/17
Number of function block global clocks used/remaining: 1/1
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
off_adj 0 FB15_1 92 I/O O
off_adj_delay 0 FB15_2 93 I/O O
(unused) 0 FB15_3 95 I/O
(unused) 0 FB15_4 96 I/O I
transmit 3 FB15_5 97 I/O O CLK
CHIPDEMUX_TRI/_n000117 2 FB15_6 (b) (b)
CHIPDEMUX_TRI/_n000118 2 FB15_7 (b) (b)
N_PZ_4371 1 FB15_8 (b) (b)
DSPDEMUX_LOAD/_n000118 2 FB15_9 (b) (b)
DSPDEMUX_LOAD/_n000117 2 FB15_10 (b) (b)
N_PZ_4208 18 FB15_11 (b) (b)
(unused) 0 FB15_12 98 I/O
(unused) 0 FB15_13 99 I/O
status_reg_load_out 2 FB15_14 100 I/O O
(unused) 0 FB15_15 101 I/O I
rec_prot 0 FB15_16 102 I/O O
Signals Used by Logic in Function Block
1: DSPDEMUX_LOAD/_n000117 14: REG_DSIQTIME_0/stored_value<2> 26: demux_chip_sel_tri<1>
2: DSPDEMUX_LOAD/_n000118 15: REG_DSIQTIME_0/stored_value<3> 27: demux_chip_sel_tri<2>
3: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 16: chip_sel_tri<7> 28: demux_chip_sel_tri<3>
4: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 17: cntr_cnt<0> 29: demux_dsp_sel_load<0>
5: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 18: cntr_cnt<1> 30: demux_dsp_sel_load<1>
6: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 19: cntr_cnt<2> 31: demux_dsp_sel_load<2>
7: FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 20: cntr_cnt<3> 32: demux_dsp_sel_load<3>
8: FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 21: cntr_cnt<4> 33: dsp_data<4>
9: FSM/SHELL1_DSP_SM_2/todsp_command0 22: cntr_cnt<5> 34: dsp_data<5>
10: FSM/SHELL1_DSP_SM_2/todsp_command1 23: cntr_cnt<6> 35: dsp_data<6>
11: N_PZ_4285 24: cntr_cnt<7> 36: dsp_data<7>
12: REG_DSIQTIME_0/stored_value<0> 25: demux_chip_sel_tri<0> 37: transmit
13: REG_DSIQTIME_0/stored_value<1>
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
off_adj ........................................ 0
off_adj_delay ........................................ 0
transmit ..XXXXX...X.....XXXXXXXX............X... 15
CHIPDEMUX_TRI/_n000117
........................XXXX............ 4
CHIPDEMUX_TRI/_n000118
........................X.XX............ 3
N_PZ_4371 .......XXX.............................. 3
DSPDEMUX_LOAD/_n000118
............................X.XX........ 3
DSPDEMUX_LOAD/_n000117
............................XXXX........ 4
N_PZ_4208 ...........XXXXXXXXXXXXX........XXXX.... 17
status_reg_load_out
XX..........................XXXX........ 6
rec_prot ........................................ 0
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB16 ***********************************
Number of function block inputs used/remaining: 33/7
Number of foldback NANDs used/remaining: 0/8
Number of function block local control terms used/remaining: 2/6
Number of PLA product terms used/remaining: 16/32
Number of function block global clocks used/remaining: 0/2
Signal Total Loc Pin Pin Pin GCK
Name Pt No. Type Use
(unused) 0 FB16_1 118 I/O I
(unused) 0 FB16_2 117 I/O I
dsp_data<31> 2 FB16_3 115 I/O I/O
dsp_data<30> 2 FB16_4 114 I/O I/O
dsp_data<29> 2 FB16_5 113 I/O I/O
(unused) 0 FB16_6 (b)
N_PZ_4458 1 FB16_7 (b) (b)
chip_sel_tri<7> 2 FB16_8 (b) (b)
dsp_sel_tri<0> 2 FB16_9 (b) (b)
DSPDEMUX_TRI/_n000117 2 FB16_10 (b) (b)
DSPDEMUX_TRI/_n000118 2 FB16_11 (b) (b)
dsp_data<28> 2 FB16_12 112 I/O I/O
dsp_data<27> 2 FB16_13 111 I/O I/O
dsp_data<26> 2 FB16_14 110 I/O I/O
dsp_data<25> 2 FB16_15 109 I/O I/O
(unused) 0 FB16_16 108 I/O
Signals Used by Logic in Function Block
1: CHIPDEMUX_TRI/_n000117 12: demux_chip_sel_tri<0> 23: dsp_data<13>.PIN
2: CHIPDEMUX_TRI/_n000118 13: demux_chip_sel_tri<1> 24: dsp_data<14>.PIN
3: DSPDEMUX_TRI/_n000117 14: demux_chip_sel_tri<2> 25: dsp_data<15>.PIN
4: DSPDEMUX_TRI/_n000118 15: demux_chip_sel_tri<3> 26: dsp_data<16>.PIN
5: data<25>.PIN 16: demux_dsp_sel_tri<0> 27: dsp_data<17>.PIN
6: data<26>.PIN 17: demux_dsp_sel_tri<1> 28: dsp_data<18>.PIN
7: data<27>.PIN 18: demux_dsp_sel_tri<2> 29: dsp_data<19>.PIN
8: data<28>.PIN 19: demux_dsp_sel_tri<3> 30: dsp_data<20>.PIN
9: data<29>.PIN 20: dsp_data<10>.PIN 31: dsp_data<21>.PIN
10: data<30>.PIN 21: dsp_data<11>.PIN 32: dsp_data<22>.PIN
11: data<31>.PIN 22: dsp_data<12>.PIN 33: dsp_data<23>.PIN
Signal 1 2 3 4 FB
Name 0----+----0----+----0----+----0----+----0 Inputs
dsp_data<31> ..........X............................. 1
dsp_data<30> .........X.............................. 1
dsp_data<29> ........X............................... 1
N_PZ_4458 ...................XXXXXXXXXXXXXX....... 14
chip_sel_tri<7> XX.........XXXX......................... 6
dsp_sel_tri<0> ..XX...........XXXX..................... 6
DSPDEMUX_TRI/_n000117
...............XXXX..................... 4
DSPDEMUX_TRI/_n000118
...............X.XX..................... 3
dsp_data<28> .......X................................ 1
dsp_data<27> ......X................................. 1
dsp_data<26> .....X.................................. 1
dsp_data<25> ....X................................... 1
0----+----1----+----2----+----3----+----4
0 0 0 0
******************************* Equations ********************************
********** Mapped Logic **********
CHIPDEMUX_TRI/_n000117 <= ((NOT demux_chip_sel_tri(0))
OR (demux_chip_sel_tri(2) AND NOT demux_chip_sel_tri(1) AND
demux_chip_sel_tri(3)));
CHIPDEMUX_TRI/_n000118 <= ((NOT demux_chip_sel_tri(0) AND NOT demux_chip_sel_tri(2))
OR (NOT demux_chip_sel_tri(0) AND NOT demux_chip_sel_tri(3)));
DSPDEMUX_LOAD/_n000117 <= ((NOT demux_dsp_sel_load(0))
OR (demux_dsp_sel_load(2) AND demux_dsp_sel_load(3) AND
NOT demux_dsp_sel_load(1)));
DSPDEMUX_LOAD/_n000118 <= ((NOT demux_dsp_sel_load(0) AND NOT demux_dsp_sel_load(2))
OR (NOT demux_dsp_sel_load(0) AND NOT demux_dsp_sel_load(3)));
DSPDEMUX_TRI/_n000117 <= ((NOT demux_dsp_sel_tri(0))
OR (demux_dsp_sel_tri(2) AND demux_dsp_sel_tri(3) AND
NOT demux_dsp_sel_tri(1)));
DSPDEMUX_TRI/_n000118 <= ((NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(2))
OR (NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(3)));
FDCPE_FSM/SHELL1_DSP_SM_2/cntr_rst: FDCPE port map (FSM/SHELL1_DSP_SM_2/cntr_rst,FSM/SHELL1_DSP_SM_2/cntr_rst_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/cntr_rst_D <= ((N_PZ_4127)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/cntr_rst)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/cntr_rst AND FSM/SHELL1_DSP_SM_2/tochip_command1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/cntr_rst)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/cntr_rst AND NOT N_PZ_4285)
OR (FSM/SHELL1_DSP_SM_2/cntr_rst AND NOT N_PZ_4285 AND
N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND N_PZ_4285 AND NOT N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4285 AND
NOT N_PZ_4398 AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND N_PZ_4126 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (cntr_cnt(0) AND FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND
NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
N_PZ_4126));
FTCPE_FSM/SHELL1_DSP_SM_2/col_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt0,FSM/SHELL1_DSP_SM_2/col_cnt0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt0_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4283)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/col_cnt0));
FTCPE_FSM/SHELL1_DSP_SM_2/col_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt1,FSM/SHELL1_DSP_SM_2/col_cnt1_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4093)
OR (N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND
N_PZ_4299 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND NOT N_PZ_4350 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt2,FSM/SHELL1_DSP_SM_2/col_cnt2_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT N_PZ_4145)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt3,FSM/SHELL1_DSP_SM_2/col_cnt3_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT N_PZ_4145)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
FSM/SHELL1_DSP_SM_2/col_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt4: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt4,FSM/SHELL1_DSP_SM_2/col_cnt4_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt4_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT N_PZ_4145)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/col_cnt5: FDCPE port map (FSM/SHELL1_DSP_SM_2/col_cnt5,FSM/SHELL1_DSP_SM_2/col_cnt5_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/col_cnt5_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (NOT FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT N_PZ_4145)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4283 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4)));
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt0,FSM/SHELL1_DSP_SM_2/ramp_cnt0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt0_T <= NOT (((N_PZ_4285)
OR (NOT N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4291)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT N_PZ_4192 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6)));
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt1,N_PZ_4192,CLK,reset,'0','1');
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt2: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt2,FSM/SHELL1_DSP_SM_2/ramp_cnt2_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt2_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt3: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt3,FSM/SHELL1_DSP_SM_2/ramp_cnt3_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt3_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt2);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt4: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt4,FSM/SHELL1_DSP_SM_2/ramp_cnt4_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt4_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt5: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt5,FSM/SHELL1_DSP_SM_2/ramp_cnt5_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt5_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt4);
FTCPE_FSM/SHELL1_DSP_SM_2/ramp_cnt6: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramp_cnt6,FSM/SHELL1_DSP_SM_2/ramp_cnt6_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramp_cnt6_T <= (FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND N_PZ_4192 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND FSM/SHELL1_DSP_SM_2/ramp_cnt5);
FTCPE_FSM/SHELL1_DSP_SM_2/ramps0: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramps0,FSM/SHELL1_DSP_SM_2/ramps0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramps0_T <= ((N_PZ_4127 AND FSM/SHELL1_DSP_SM_2/ramps0)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND NOT N_PZ_4127));
FTCPE_FSM/SHELL1_DSP_SM_2/ramps1: FTCPE port map (FSM/SHELL1_DSP_SM_2/ramps1,FSM/SHELL1_DSP_SM_2/ramps1_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/ramps1_T <= ((N_PZ_4127 AND FSM/SHELL1_DSP_SM_2/ramps1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
FSM/SHELL1_DSP_SM_2/ramps0));
FTCPE_FSM/SHELL1_DSP_SM_2/row_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt0,FSM/SHELL1_DSP_SM_2/row_cnt0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/row_cnt0_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/row_cnt0)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
FTCPE_FSM/SHELL1_DSP_SM_2/row_cnt1: FTCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt1,FSM/SHELL1_DSP_SM_2/row_cnt1_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/row_cnt1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/row_cnt1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/row_cnt0)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
FSM/SHELL1_DSP_SM_2/row_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND FSM/SHELL1_DSP_SM_2/col_cnt2 AND
FSM/SHELL1_DSP_SM_2/col_cnt3 AND FSM/SHELL1_DSP_SM_2/col_cnt4 AND
FSM/SHELL1_DSP_SM_2/col_cnt5));
FDCPE_FSM/SHELL1_DSP_SM_2/row_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt2,FSM/SHELL1_DSP_SM_2/row_cnt2_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/row_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt2)
OR (NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT N_PZ_4387)
OR (FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt2 AND N_PZ_4387)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)));
FDCPE_FSM/SHELL1_DSP_SM_2/row_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/row_cnt3,FSM/SHELL1_DSP_SM_2/row_cnt3_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/row_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (NOT N_PZ_4387 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
OR (FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt2 AND N_PZ_4387 AND FSM/SHELL1_DSP_SM_2/row_cnt3)));
FTCPE_FSM/SHELL1_DSP_SM_2/sel_cnt0: FTCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt0,FSM/SHELL1_DSP_SM_2/sel_cnt0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sel_cnt0_T <= ((FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4190)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4093 AND
NOT N_PZ_4190)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/sel_cnt0)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND N_PZ_4093 AND NOT N_PZ_4190)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt1,FSM/SHELL1_DSP_SM_2/sel_cnt1_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sel_cnt1_D <= NOT (((FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190)
OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND NOT N_PZ_4190)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt2,FSM/SHELL1_DSP_SM_2/sel_cnt2_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sel_cnt2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt1)
OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT N_PZ_4190)
OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sel_cnt3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sel_cnt3,FSM/SHELL1_DSP_SM_2/sel_cnt3_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sel_cnt3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (NOT N_PZ_4190 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
FSM/SHELL1_DSP_SM_2/sel_cnt1 AND N_PZ_4190 AND FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4208)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND N_PZ_4285 AND cntr_cnt(1) AND
cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND
NOT cntr_cnt(6) AND NOT cntr_cnt(7))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND N_PZ_4285 AND NOT cntr_cnt(1) AND
NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4126)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4208)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4126 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3_D <= NOT (((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4291)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND
N_PZ_4285 AND cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND
NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7))));
FTCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4: FTCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4_T <= ((N_PZ_4350 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND NOT N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND NOT N_PZ_4126)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398 AND N_PZ_4126)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND N_PZ_4285 AND cntr_cnt(1) AND
cntr_cnt(3) AND cntr_cnt(2) AND NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND
NOT cntr_cnt(6) AND NOT cntr_cnt(7))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND N_PZ_4285 AND NOT cntr_cnt(1) AND
NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5,FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5_D,CLK,'0',reset,'1');
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5_D <= NOT (((N_PZ_4127)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4187)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4187)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4126)
OR (N_PZ_4350 AND NOT N_PZ_4299 AND N_PZ_4093)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4187)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
NOT N_PZ_4126 AND N_PZ_4291)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1_D <= ((fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354));
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 <= (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458 AND
NOT dsp_data(0).PIN);
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
OR (NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2-In93 AND
N_PZ_4253)));
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51 <= (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458);
FDCPE_FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3: FDCPE port map (FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3,FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3_D,CLK,'0',reset,'1');
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_FSM/SHELL1_DSP_SM_2/tochip_command0: FDCPE port map (FSM/SHELL1_DSP_SM_2/tochip_command0,FSM/SHELL1_DSP_SM_2/tochip_command0_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/tochip_command0_D <= ((fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND FSM/SHELL1_DSP_SM_2/tochip_command0)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND
FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT dsp_are_l));
FDCPE_FSM/SHELL1_DSP_SM_2/tochip_command1: FDCPE port map (FSM/SHELL1_DSP_SM_2/tochip_command1,FSM/SHELL1_DSP_SM_2/tochip_command1_D,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/tochip_command1_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
OR (FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT dsp_awe_l AND
NOT dsp_asm2_l AND NOT fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
OR (FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT dsp_asm2_l AND
NOT fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354 AND NOT dsp_data(0).PIN));
FTCPE_FSM/SHELL1_DSP_SM_2/todsp_command0: FTCPE port map (FSM/SHELL1_DSP_SM_2/todsp_command0,FSM/SHELL1_DSP_SM_2/todsp_command0_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/todsp_command0_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/todsp_command0)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
FSM/SHELL1_DSP_SM_2/todsp_command0));
FTCPE_FSM/SHELL1_DSP_SM_2/todsp_command1: FTCPE port map (FSM/SHELL1_DSP_SM_2/todsp_command1,FSM/SHELL1_DSP_SM_2/todsp_command1_T,CLK,reset,'0','1');
FSM/SHELL1_DSP_SM_2/todsp_command1_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/todsp_command1 AND N_PZ_4285)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT FSM/SHELL1_DSP_SM_2/todsp_command1 AND
NOT FSM/SHELL1_DSP_SM_2/tochip_command0));
N_PZ_4093 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4));
N_PZ_4112 <= ((N_PZ_4285)
OR (NOT N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6));
N_PZ_4126 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
FSM/SHELL1_DSP_SM_2/row_cnt3));
N_PZ_4127 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4208));
N_PZ_4145 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4093 AND
FSM/SHELL1_DSP_SM_2/col_cnt1)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/col_cnt0 AND N_PZ_4299 AND N_PZ_4093 AND
FSM/SHELL1_DSP_SM_2/col_cnt1));
N_PZ_4187 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4126)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
FSM/SHELL1_DSP_SM_2/row_cnt3));
N_PZ_4190 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/sel_cnt0)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/tochip_command1 AND
NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND FSM/SHELL1_DSP_SM_2/sel_cnt0));
N_PZ_4192 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND
NOT N_PZ_4350 AND FSM/SHELL1_DSP_SM_2/ramp_cnt0)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4291 AND FSM/SHELL1_DSP_SM_2/ramp_cnt0));
N_PZ_4208 <= NOT chip_sel_tri(7)
XOR ((cntr_cnt(0) AND chip_sel_tri(7) AND
NOT REG_DSIQTIME_0/stored_value(0))
OR (NOT cntr_cnt(0) AND chip_sel_tri(7) AND
REG_DSIQTIME_0/stored_value(0))
OR (chip_sel_tri(7) AND cntr_cnt(1) AND
NOT REG_DSIQTIME_0/stored_value(1))
OR (chip_sel_tri(7) AND NOT cntr_cnt(1) AND
REG_DSIQTIME_0/stored_value(1))
OR (chip_sel_tri(7) AND cntr_cnt(3) AND
NOT REG_DSIQTIME_0/stored_value(3))
OR (chip_sel_tri(7) AND NOT cntr_cnt(3) AND
REG_DSIQTIME_0/stored_value(3))
OR (chip_sel_tri(7) AND cntr_cnt(2) AND
NOT REG_DSIQTIME_0/stored_value(2))
OR (chip_sel_tri(7) AND NOT cntr_cnt(2) AND
REG_DSIQTIME_0/stored_value(2))
OR (chip_sel_tri(7) AND cntr_cnt(4) AND
NOT REG_DSIQTIME_0/stored_value(4))
OR (chip_sel_tri(7) AND NOT cntr_cnt(4) AND
REG_DSIQTIME_0/stored_value(4))
OR (chip_sel_tri(7) AND cntr_cnt(5) AND
NOT REG_DSIQTIME_0/stored_value(5))
OR (chip_sel_tri(7) AND NOT cntr_cnt(5) AND
REG_DSIQTIME_0/stored_value(5))
OR (chip_sel_tri(7) AND cntr_cnt(6) AND
NOT REG_DSIQTIME_0/stored_value(6))
OR (chip_sel_tri(7) AND NOT cntr_cnt(6) AND
REG_DSIQTIME_0/stored_value(6))
OR (chip_sel_tri(7) AND cntr_cnt(7) AND
NOT REG_DSIQTIME_0/stored_value(7))
OR (chip_sel_tri(7) AND NOT cntr_cnt(7) AND
REG_DSIQTIME_0/stored_value(7))
OR (cntr_cnt(0) AND NOT chip_sel_tri(7) AND cntr_cnt(1) AND
cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND cntr_cnt(5) AND
cntr_cnt(6) AND cntr_cnt(7)));
N_PZ_4253 <= ((NOT dsp_are_l)
OR (NOT dsp_awe_l AND NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458));
N_PZ_4283 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND
N_PZ_4299));
N_PZ_4285 <= (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3);
N_PZ_4291 <= (FSM/SHELL1_DSP_SM_2/ramps0 AND
NOT FSM/SHELL1_DSP_SM_2/ramps1);
N_PZ_4299 <= (NOT FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3);
N_PZ_4324 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354));
N_PZ_4326 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT N_PZ_4371)
OR (fake_transmit AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2)
OR (NOT dsp_asm2_l AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51));
N_PZ_4350 <= (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3);
N_PZ_4354 <= (NOT dsp_data(8).PIN AND NOT dsp_data(7).PIN AND
NOT dsp_data(6).PIN AND NOT dsp_data(5).PIN AND NOT dsp_data(4).PIN AND
NOT dsp_data(3).PIN AND NOT dsp_data(2).PIN AND NOT dsp_data(1).PIN AND
NOT dsp_data(9).PIN AND NOT dsp_data(24).PIN AND NOT dsp_data(31).PIN AND
NOT dsp_data(30).PIN AND NOT dsp_data(29).PIN AND NOT dsp_data(28).PIN AND
NOT dsp_data(27).PIN AND NOT dsp_data(26).PIN AND NOT dsp_data(25).PIN AND NOT dsp_add(0) AND
NOT dsp_add(1) AND NOT dsp_add(3) AND NOT dsp_add(2) AND N_PZ_4458);
N_PZ_4371 <= (NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/todsp_command1 AND NOT FSM/SHELL1_DSP_SM_2/todsp_command0);
N_PZ_4387 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
FSM/SHELL1_DSP_SM_2/row_cnt1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND
FSM/SHELL1_DSP_SM_2/row_cnt1));
N_PZ_4398 <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350));
N_PZ_4399 <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
N_PZ_4401 <= ((N_PZ_4187)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5));
N_PZ_4458 <= (NOT dsp_data(16).PIN AND NOT dsp_data(15).PIN AND
NOT dsp_data(14).PIN AND NOT dsp_data(13).PIN AND NOT dsp_data(12).PIN AND
NOT dsp_data(11).PIN AND NOT dsp_data(10).PIN AND NOT dsp_data(23).PIN AND
NOT dsp_data(22).PIN AND NOT dsp_data(21).PIN AND NOT dsp_data(20).PIN AND
NOT dsp_data(19).PIN AND NOT dsp_data(18).PIN AND NOT dsp_data(17).PIN);
N_PZ_4460 <= (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6);
FDCPE_PRE: FDCPE port map (PRE,PRE_D,CLK,reset,'0','1');
PRE_D <= NOT (((NOT PRE AND N_PZ_4401)
OR (NOT PRE AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
OR (NOT PRE AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
N_PZ_4299)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND N_PZ_4187)));
LDCP_REG_DSIQTIME_0/stored_value0: LDCP port map (REG_DSIQTIME_0/stored_value(0),dsp_data(0).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value1: LDCP port map (REG_DSIQTIME_0/stored_value(1),dsp_data(1).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value2: LDCP port map (REG_DSIQTIME_0/stored_value(2),dsp_data(2).PIN,status_reg_load_out,'0','0');
LDCP_REG_DSIQTIME_0/stored_value3: LDCP port map (REG_DSIQTIME_0/stored_value(3),dsp_data(3).PIN,status_reg_load_out,'0','0');
LDCP_dsp_data4: LDCP port map (dsp_data(4),'0');
dsp_data(4) <= dsp_data_I(4) when dsp_data_OE(4) = '1' else 'Z';
dsp_data_OE(4) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value4: FDCPE port map (REG_DSIQTIME_0/stored_value(4),dsp_data(4).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data5: LDCP port map (dsp_data(5),'0');
dsp_data(5) <= dsp_data_I(5) when dsp_data_OE(5) = '1' else 'Z';
dsp_data_OE(5) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value5: FDCPE port map (REG_DSIQTIME_0/stored_value(5),dsp_data(5).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data6: LDCP port map (dsp_data(6),'0');
dsp_data(6) <= dsp_data_I(6) when dsp_data_OE(6) = '1' else 'Z';
dsp_data_OE(6) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value6: FDCPE port map (REG_DSIQTIME_0/stored_value(6),dsp_data(6).PIN,status_reg_load_out,'0','0','1');
LDCP_dsp_data7: LDCP port map (dsp_data(7),'0');
dsp_data(7) <= dsp_data_I(7) when dsp_data_OE(7) = '1' else 'Z';
dsp_data_OE(7) <= dsp_sel_tri(0);FDCPE_REG_DSIQTIME_0/stored_value7: FDCPE port map (REG_DSIQTIME_0/stored_value(7),dsp_data(7).PIN,status_reg_load_out,'0','0','1');
FDCPE_SAN_BUFR: FDCPE port map (SAN_BUFR,SAN_BUFR_D,CLK,reset,'0','1');
SAN_BUFR_D <= ((N_PZ_4283 AND SAN_BUFR)
OR (N_PZ_4187 AND SAN_BUFR)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4093 AND
SAN_BUFR)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND
SAN_BUFR)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND
SAN_BUFR)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND
NOT N_PZ_4398 AND SAN_BUFR)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398 AND N_PZ_4187)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND SAN_BUFR));
SAN <= SAN_BUFR;
FDCPE_SH_samp_0: FDCPE port map (SH_samp_0,SH_samp_0_D,CLK,reset,'0','1');
SH_samp_0_D <= ((NOT N_PZ_4127 AND SH_samp_0)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4208 AND NOT SH_samp_0));
SH_samp_1 <= '0';
SH_samp_2 <= '0';
SH_samp_3 <= '0';
VREG_EN_l <= '0';
FDCPE_chip_sel1: FDCPE port map (chip_sel(1),chip_sel_D(1),CLK,reset,'0','1');
chip_sel_D(1) <= NOT (((N_PZ_4285 AND NOT chip_sel(1))
OR (N_PZ_4093 AND NOT chip_sel(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT chip_sel(1))
OR (N_PZ_4350 AND NOT N_PZ_4127 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND N_PZ_4285)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND NOT N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/tochip_command0 AND NOT N_PZ_4350)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4350 AND
NOT N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND FSM/SHELL1_DSP_SM_2/col_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT chip_sel(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND
FSM/SHELL1_DSP_SM_2/row_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt3)));
chip_sel(2) <= '0';
chip_sel(3) <= '0';
chip_sel(4) <= '0';
chip_sel(5) <= '0';
chip_sel(6) <= '0';
chip_sel(7) <= '0';
chip_sel(8) <= '0';
chip_sel(9) <= '0';
chip_sel(10) <= '0';
chip_sel(11) <= '0';
chip_sel(12) <= '0';
LDCP_chip_sel_tri7: LDCP port map (chip_sel_tri(7),chip_sel_tri_D(7),NOT ,'0','0');
chip_sel_tri_D(7) <= (demux_chip_sel_tri(0) AND demux_chip_sel_tri(2) AND
demux_chip_sel_tri(1) AND NOT demux_chip_sel_tri(3));
FDCPE_cntr_8: FDCPE port map (cntr_8,cntr_8_D,CLK,reset,'0','1');
cntr_8_D <= ((NOT N_PZ_4127 AND cntr_8)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460 AND
NOT cntr_8));
FDCPE_cntr_9: FDCPE port map (cntr_9,cntr_9_D,CLK,reset,'0','1');
cntr_9_D <= ((NOT N_PZ_4127 AND cntr_9)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4460 AND
NOT cntr_9));
FDCPE_cntr_cnt0: FDCPE port map (cntr_cnt(0),cntr_cnt_D(0),CLK,'0','0','1');
cntr_cnt_D(0) <= (NOT cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst);
FDCPE_cntr_cnt1: FDCPE port map (cntr_cnt(1),cntr_cnt_D(1),CLK,'0','0','1');
cntr_cnt_D(1) <= ((cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
NOT cntr_cnt(1))
OR (NOT cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1)));
FTCPE_cntr_cnt2: FTCPE port map (cntr_cnt(2),cntr_cnt_T(2),CLK,'0','0','1');
cntr_cnt_T(2) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(2))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1)));
FTCPE_cntr_cnt3: FTCPE port map (cntr_cnt(3),cntr_cnt_T(3),CLK,'0','0','1');
cntr_cnt_T(3) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(3))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(2)));
FTCPE_cntr_cnt4: FTCPE port map (cntr_cnt(4),cntr_cnt_T(4),CLK,'0','0','1');
cntr_cnt_T(4) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(4))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2)));
FTCPE_cntr_cnt5: FTCPE port map (cntr_cnt(5),cntr_cnt_T(5),CLK,'0','0','1');
cntr_cnt_T(5) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(5))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4)));
FTCPE_cntr_cnt6: FTCPE port map (cntr_cnt(6),cntr_cnt_T(6),CLK,'0','0','1');
cntr_cnt_T(6) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(6))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND
cntr_cnt(5)));
FTCPE_cntr_cnt7: FTCPE port map (cntr_cnt(7),cntr_cnt_T(7),CLK,'0','0','1');
cntr_cnt_T(7) <= ((FSM/SHELL1_DSP_SM_2/cntr_rst AND cntr_cnt(7))
OR (cntr_cnt(0) AND NOT FSM/SHELL1_DSP_SM_2/cntr_rst AND
cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND
cntr_cnt(5) AND cntr_cnt(6)));
FDCPE_cntr_sel: FDCPE port map (cntr_sel,cntr_sel_D,CLK,reset,'0','1');
cntr_sel_D <= NOT ((NOT cntr_sel AND N_PZ_4112));
FDCPE_cntr_set_value0: FDCPE port map (cntr_set_value(0),cntr_set_value_D(0),CLK,reset,'0','1');
cntr_set_value_D(0) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(0))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)));
FDCPE_cntr_set_value1: FDCPE port map (cntr_set_value(1),cntr_set_value_D(1),CLK,reset,'0','1');
cntr_set_value_D(1) <= ((N_PZ_4112 AND cntr_set_value(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4398)
OR (N_PZ_4350 AND N_PZ_4398 AND N_PZ_4291));
FDCPE_cntr_set_value2: FDCPE port map (cntr_set_value(2),cntr_set_value_D(2),CLK,reset,'0','1');
cntr_set_value_D(2) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)));
FDCPE_cntr_set_value3: FDCPE port map (cntr_set_value(3),cntr_set_value_D(3),CLK,reset,'0','1');
cntr_set_value_D(3) <= ((N_PZ_4285 AND cntr_set_value(3))
OR (NOT N_PZ_4398 AND cntr_set_value(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND
cntr_set_value(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4291)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6 AND cntr_set_value(3)));
FDCPE_cntr_set_value5: FDCPE port map (cntr_set_value(5),cntr_set_value_D(5),CLK,reset,'0','1');
cntr_set_value_D(5) <= ((N_PZ_4112 AND cntr_set_value(5))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350));
FDCPE_cntr_set_value6: FDCPE port map (cntr_set_value(6),cntr_set_value_D(6),CLK,reset,'0','1');
cntr_set_value_D(6) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(6))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4291)));
FDCPE_cntr_set_value7: FDCPE port map (cntr_set_value(7),cntr_set_value_D(7),CLK,reset,'0','1');
cntr_set_value_D(7) <= NOT (((N_PZ_4112 AND NOT cntr_set_value(7))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4291)));
FDCPE_cntr_tri: FDCPE port map (cntr_tri,cntr_tri_D,CLK,reset,'0','1');
cntr_tri_D <= ((N_PZ_4127)
OR (N_PZ_4401 AND cntr_tri)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_tri)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4299 AND
cntr_tri)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND NOT N_PZ_4291)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND N_PZ_4398)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4187)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4460 AND N_PZ_4187));
FDCPE_col_clk: FDCPE port map (col_clk,col_clk_D,CLK,reset,'0','1');
col_clk_D <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND col_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4093 AND
col_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4187 AND
col_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND
col_clk)
OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4350 AND col_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4187 AND col_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
NOT N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND
FSM/SHELL1_DSP_SM_2/sel_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt3 AND N_PZ_4187)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND col_clk));
FTCPE_col_pulse: FTCPE port map (col_pulse,col_pulse_T,CLK,reset,'0','1');
col_pulse_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
col_pulse)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT col_pulse));
FDCPE_comp_sleep: FDCPE port map (comp_sleep,comp_sleep_D,CLK,'0',reset,'1');
comp_sleep_D <= ((NOT N_PZ_4127 AND comp_sleep)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4291 AND NOT comp_sleep));
dac_clk <= CLK;
dac_cs_l <= '0';
FDCPE_dac_en: FDCPE port map (dac_en,dac_en_D,CLK,reset,'0','1');
dac_en_D <= NOT ((NOT N_PZ_4127 AND NOT dac_en));
dac_pd <= '0';
data_I(0) <= data(8);
data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
data_OE(0) <= cntr_tri;
data_I(1) <= data(9);
data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
data_OE(1) <= cntr_tri;
data_I(2) <= NOT (((NOT cntr_cnt(2) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(2))));
data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
data_OE(2) <= cntr_tri;
data_I(3) <= NOT (((NOT cntr_cnt(3) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(3))));
data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
data_OE(3) <= cntr_tri;
data_I(4) <= (cntr_cnt(4) AND NOT cntr_sel);
data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
data_OE(4) <= cntr_tri;
data_I(5) <= NOT (((NOT cntr_cnt(5) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(5))));
data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
data_OE(5) <= cntr_tri;
data_I(6) <= NOT (((NOT cntr_cnt(6) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(6))));
data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
data_OE(6) <= cntr_tri;
data_I(7) <= NOT (((NOT cntr_cnt(7) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(7))));
data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
data_OE(7) <= cntr_tri;
data_I(8) <= NOT (((NOT cntr_cnt(0) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(0))));
data(8) <= data_I(8) when data_OE(8) = '1' else 'Z';
data_OE(8) <= cntr_tri;
data_I(9) <= NOT (((NOT cntr_cnt(1) AND NOT cntr_sel)
OR (cntr_sel AND NOT cntr_set_value(1))));
data(9) <= data_I(9) when data_OE(9) = '1' else 'Z';
data_OE(9) <= cntr_tri;
data_I(10) <= data(2);
data(10) <= data_I(10) when data_OE(10) = '1' else 'Z';
data_OE(10) <= cntr_tri;
data_I(11) <= data(3);
data(11) <= data_I(11) when data_OE(11) = '1' else 'Z';
data_OE(11) <= cntr_tri;
data_I(12) <= data(4);
data(12) <= data_I(12) when data_OE(12) = '1' else 'Z';
data_OE(12) <= cntr_tri;
data_I(13) <= data(5);
data(13) <= data_I(13) when data_OE(13) = '1' else 'Z';
data_OE(13) <= cntr_tri;
data_I(14) <= data(6);
data(14) <= data_I(14) when data_OE(14) = '1' else 'Z';
data_OE(14) <= cntr_tri;
data_I(15) <= data(7);
data(15) <= data_I(15) when data_OE(15) = '1' else 'Z';
data_OE(15) <= cntr_tri;
data_I(16) <= data(8);
data(16) <= data_I(16) when data_OE(16) = '1' else 'Z';
data_OE(16) <= cntr_tri;
data_I(17) <= data(9);
data(17) <= data_I(17) when data_OE(17) = '1' else 'Z';
data_OE(17) <= cntr_tri;
data_I(18) <= data(2);
data(18) <= data_I(18) when data_OE(18) = '1' else 'Z';
data_OE(18) <= cntr_tri;
data_I(19) <= data(3);
data(19) <= data_I(19) when data_OE(19) = '1' else 'Z';
data_OE(19) <= cntr_tri;
data_I(20) <= data(4);
data(20) <= data_I(20) when data_OE(20) = '1' else 'Z';
data_OE(20) <= cntr_tri;
data_I(21) <= data(5);
data(21) <= data_I(21) when data_OE(21) = '1' else 'Z';
data_OE(21) <= cntr_tri;
data_I(22) <= data(6);
data(22) <= data_I(22) when data_OE(22) = '1' else 'Z';
data_OE(22) <= cntr_tri;
data_I(23) <= data(7);
data(23) <= data_I(23) when data_OE(23) = '1' else 'Z';
data_OE(23) <= cntr_tri;
data_I(24) <= data(8);
data(24) <= data_I(24) when data_OE(24) = '1' else 'Z';
data_OE(24) <= cntr_tri;
data_I(25) <= data(9);
data(25) <= data_I(25) when data_OE(25) = '1' else 'Z';
data_OE(25) <= cntr_tri;
data_I(26) <= data(2);
data(26) <= data_I(26) when data_OE(26) = '1' else 'Z';
data_OE(26) <= cntr_tri;
data_I(27) <= data(3);
data(27) <= data_I(27) when data_OE(27) = '1' else 'Z';
data_OE(27) <= cntr_tri;
data_I(28) <= data(4);
data(28) <= data_I(28) when data_OE(28) = '1' else 'Z';
data_OE(28) <= cntr_tri;
data_I(29) <= data(5);
data(29) <= data_I(29) when data_OE(29) = '1' else 'Z';
data_OE(29) <= cntr_tri;
data_I(30) <= data(6);
data(30) <= data_I(30) when data_OE(30) = '1' else 'Z';
data_OE(30) <= cntr_tri;
data_I(31) <= data(7);
data(31) <= data_I(31) when data_OE(31) = '1' else 'Z';
data_OE(31) <= cntr_tri;
FTCPE_demux_chip_sel_tri0: FTCPE port map (demux_chip_sel_tri(0),demux_chip_sel_tri_T(0),CLK,reset,'0','1');
demux_chip_sel_tri_T(0) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(0))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4208 AND demux_chip_sel_tri(0))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT demux_chip_sel_tri(0) AND NOT cntr_cnt(1) AND
NOT cntr_cnt(3) AND cntr_cnt(2) AND cntr_cnt(4) AND NOT cntr_cnt(5) AND
NOT cntr_cnt(6) AND NOT cntr_cnt(7)));
FTCPE_demux_chip_sel_tri1: FTCPE port map (demux_chip_sel_tri(1),demux_chip_sel_tri_T(1),CLK,reset,'0','1');
demux_chip_sel_tri_T(1) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4208 AND demux_chip_sel_tri(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
NOT demux_chip_sel_tri(1)));
FTCPE_demux_chip_sel_tri2: FTCPE port map (demux_chip_sel_tri(2),demux_chip_sel_tri_T(2),CLK,reset,'0','1');
demux_chip_sel_tri_T(2) <= ((N_PZ_4127 AND NOT demux_chip_sel_tri(2))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT N_PZ_4208 AND demux_chip_sel_tri(2))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
NOT demux_chip_sel_tri(2)));
FTCPE_demux_chip_sel_tri3: FTCPE port map (demux_chip_sel_tri(3),demux_chip_sel_tri_T(3),CLK,reset,'0','1');
demux_chip_sel_tri_T(3) <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND NOT demux_chip_sel_tri(3))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
demux_chip_sel_tri(3)));
FDCPE_demux_dsp_sel_load0: FDCPE port map (demux_dsp_sel_load(0),demux_dsp_sel_load_D(0),CLK,'0',reset,'1');
demux_dsp_sel_load_D(0) <= NOT (((NOT demux_dsp_sel_load(0) AND N_PZ_4326)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(0))));
FDCPE_demux_dsp_sel_load1: FDCPE port map (demux_dsp_sel_load(1),demux_dsp_sel_load_D(1),CLK,'0',reset,'1');
demux_dsp_sel_load_D(1) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(1))
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(1))));
FDCPE_demux_dsp_sel_load2: FDCPE port map (demux_dsp_sel_load(2),demux_dsp_sel_load_D(2),CLK,'0',reset,'1');
demux_dsp_sel_load_D(2) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(2))
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(2))));
FDCPE_demux_dsp_sel_load3: FDCPE port map (demux_dsp_sel_load(3),demux_dsp_sel_load_D(3),CLK,'0',reset,'1');
demux_dsp_sel_load_D(3) <= NOT (((N_PZ_4326 AND NOT demux_dsp_sel_load(3))
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND N_PZ_4354)
OR (NOT dsp_awe_l AND NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND dsp_are_l AND NOT N_PZ_4354 AND NOT dsp_add(3))));
FDCPE_demux_dsp_sel_tri0: FDCPE port map (demux_dsp_sel_tri(0),demux_dsp_sel_tri_D(0),CLK,'0',reset,'1');
demux_dsp_sel_tri_D(0) <= NOT (((NOT demux_dsp_sel_tri(0) AND N_PZ_4324)
OR (NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(0) AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri1: FDCPE port map (demux_dsp_sel_tri(1),demux_dsp_sel_tri_D(1),CLK,'0',reset,'1');
demux_dsp_sel_tri_D(1) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(1))
OR (NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(1) AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri2: FDCPE port map (demux_dsp_sel_tri(2),demux_dsp_sel_tri_D(2),CLK,'0',reset,'1');
demux_dsp_sel_tri_D(2) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(2))
OR (NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(2) AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
FDCPE_demux_dsp_sel_tri3: FDCPE port map (demux_dsp_sel_tri(3),demux_dsp_sel_tri_D(3),CLK,'0',reset,'1');
demux_dsp_sel_tri_D(3) <= NOT (((N_PZ_4324 AND NOT demux_dsp_sel_tri(3))
OR (NOT dsp_asm2_l AND NOT fake_transmit AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd2 AND NOT dsp_are_l AND NOT dsp_add(3) AND
NOT FSM/SHELL1_DSP_SM_2/sreg_dsp_FFd3-In51)));
LDCP_dsp_data0: LDCP port map (dsp_data_I(0),status_reg_data(0),status_reg_load,'0','0');
dsp_data(0) <= dsp_data_I(0) when dsp_data_OE(0) = '1' else 'Z';
dsp_data_OE(0) <= dsp_sel_tri(0);
LDCP_dsp_data1: LDCP port map (dsp_data_I(1),status_reg_data(1),status_reg_load,'0','0');
dsp_data(1) <= dsp_data_I(1) when dsp_data_OE(1) = '1' else 'Z';
dsp_data_OE(1) <= dsp_sel_tri(0);
LDCP_dsp_data2: LDCP port map (dsp_data_I(2),status_reg_data(2),status_reg_load,'0','0');
dsp_data(2) <= dsp_data_I(2) when dsp_data_OE(2) = '1' else 'Z';
dsp_data_OE(2) <= dsp_sel_tri(0);
LDCP_dsp_data3: LDCP port map (dsp_data_I(3),status_reg_data(3),status_reg_load,'0','0');
dsp_data(3) <= dsp_data_I(3) when dsp_data_OE(3) = '1' else 'Z';
dsp_data_OE(3) <= dsp_sel_tri(0);
LDCP_dsp_data8: LDCP port map (dsp_data_I(8),data(8).PIN,sample_reg_load,'0','0');
dsp_data(8) <= dsp_data_I(8) when dsp_data_OE(8) = '1' else 'Z';
dsp_data_OE(8) <= '0';
LDCP_dsp_data9: LDCP port map (dsp_data_I(9),data(9).PIN,sample_reg_load,'0','0');
dsp_data(9) <= dsp_data_I(9) when dsp_data_OE(9) = '1' else 'Z';
dsp_data_OE(9) <= '0';
LDCP_dsp_data10: LDCP port map (dsp_data_I(10),data(10).PIN,sample_reg_load,'0','0');
dsp_data(10) <= dsp_data_I(10) when dsp_data_OE(10) = '1' else 'Z';
dsp_data_OE(10) <= '0';
LDCP_dsp_data11: LDCP port map (dsp_data_I(11),data(11).PIN,sample_reg_load,'0','0');
dsp_data(11) <= dsp_data_I(11) when dsp_data_OE(11) = '1' else 'Z';
dsp_data_OE(11) <= '0';
LDCP_dsp_data12: LDCP port map (dsp_data_I(12),data(12).PIN,sample_reg_load,'0','0');
dsp_data(12) <= dsp_data_I(12) when dsp_data_OE(12) = '1' else 'Z';
dsp_data_OE(12) <= '0';
LDCP_dsp_data13: LDCP port map (dsp_data_I(13),data(13).PIN,sample_reg_load,'0','0');
dsp_data(13) <= dsp_data_I(13) when dsp_data_OE(13) = '1' else 'Z';
dsp_data_OE(13) <= '0';
LDCP_dsp_data14: LDCP port map (dsp_data_I(14),data(14).PIN,sample_reg_load,'0','0');
dsp_data(14) <= dsp_data_I(14) when dsp_data_OE(14) = '1' else 'Z';
dsp_data_OE(14) <= '0';
LDCP_dsp_data15: LDCP port map (dsp_data_I(15),data(15).PIN,sample_reg_load,'0','0');
dsp_data(15) <= dsp_data_I(15) when dsp_data_OE(15) = '1' else 'Z';
dsp_data_OE(15) <= '0';
LDCP_dsp_data16: LDCP port map (dsp_data_I(16),data(16).PIN,sample_reg_load,'0','0');
dsp_data(16) <= dsp_data_I(16) when dsp_data_OE(16) = '1' else 'Z';
dsp_data_OE(16) <= '0';
LDCP_dsp_data17: LDCP port map (dsp_data_I(17),data(17).PIN,sample_reg_load,'0','0');
dsp_data(17) <= dsp_data_I(17) when dsp_data_OE(17) = '1' else 'Z';
dsp_data_OE(17) <= '0';
LDCP_dsp_data18: LDCP port map (dsp_data_I(18),data(18).PIN,sample_reg_load,'0','0');
dsp_data(18) <= dsp_data_I(18) when dsp_data_OE(18) = '1' else 'Z';
dsp_data_OE(18) <= '0';
LDCP_dsp_data19: LDCP port map (dsp_data_I(19),data(19).PIN,sample_reg_load,'0','0');
dsp_data(19) <= dsp_data_I(19) when dsp_data_OE(19) = '1' else 'Z';
dsp_data_OE(19) <= '0';
LDCP_dsp_data20: LDCP port map (dsp_data_I(20),data(20).PIN,sample_reg_load,'0','0');
dsp_data(20) <= dsp_data_I(20) when dsp_data_OE(20) = '1' else 'Z';
dsp_data_OE(20) <= '0';
LDCP_dsp_data21: LDCP port map (dsp_data_I(21),data(21).PIN,sample_reg_load,'0','0');
dsp_data(21) <= dsp_data_I(21) when dsp_data_OE(21) = '1' else 'Z';
dsp_data_OE(21) <= '0';
LDCP_dsp_data22: LDCP port map (dsp_data_I(22),data(22).PIN,sample_reg_load,'0','0');
dsp_data(22) <= dsp_data_I(22) when dsp_data_OE(22) = '1' else 'Z';
dsp_data_OE(22) <= '0';
LDCP_dsp_data23: LDCP port map (dsp_data_I(23),data(23).PIN,sample_reg_load,'0','0');
dsp_data(23) <= dsp_data_I(23) when dsp_data_OE(23) = '1' else 'Z';
dsp_data_OE(23) <= '0';
LDCP_dsp_data24: LDCP port map (dsp_data_I(24),data(24).PIN,sample_reg_load,'0','0');
dsp_data(24) <= dsp_data_I(24) when dsp_data_OE(24) = '1' else 'Z';
dsp_data_OE(24) <= '0';
LDCP_dsp_data25: LDCP port map (dsp_data_I(25),data(25).PIN,sample_reg_load,'0','0');
dsp_data(25) <= dsp_data_I(25) when dsp_data_OE(25) = '1' else 'Z';
dsp_data_OE(25) <= '0';
LDCP_dsp_data26: LDCP port map (dsp_data_I(26),data(26).PIN,sample_reg_load,'0','0');
dsp_data(26) <= dsp_data_I(26) when dsp_data_OE(26) = '1' else 'Z';
dsp_data_OE(26) <= '0';
LDCP_dsp_data27: LDCP port map (dsp_data_I(27),data(27).PIN,sample_reg_load,'0','0');
dsp_data(27) <= dsp_data_I(27) when dsp_data_OE(27) = '1' else 'Z';
dsp_data_OE(27) <= '0';
LDCP_dsp_data28: LDCP port map (dsp_data_I(28),data(28).PIN,sample_reg_load,'0','0');
dsp_data(28) <= dsp_data_I(28) when dsp_data_OE(28) = '1' else 'Z';
dsp_data_OE(28) <= '0';
LDCP_dsp_data29: LDCP port map (dsp_data_I(29),data(29).PIN,sample_reg_load,'0','0');
dsp_data(29) <= dsp_data_I(29) when dsp_data_OE(29) = '1' else 'Z';
dsp_data_OE(29) <= '0';
LDCP_dsp_data30: LDCP port map (dsp_data_I(30),data(30).PIN,sample_reg_load,'0','0');
dsp_data(30) <= dsp_data_I(30) when dsp_data_OE(30) = '1' else 'Z';
dsp_data_OE(30) <= '0';
LDCP_dsp_data31: LDCP port map (dsp_data_I(31),data(31).PIN,sample_reg_load,'0','0');
dsp_data(31) <= dsp_data_I(31) when dsp_data_OE(31) = '1' else 'Z';
dsp_data_OE(31) <= '0';
LDCP_dsp_sel_tri0: LDCP port map (dsp_sel_tri(0),dsp_sel_tri_D(0),NOT ,'0','0');
dsp_sel_tri_D(0) <= (NOT demux_dsp_sel_tri(0) AND NOT demux_dsp_sel_tri(2) AND
NOT demux_dsp_sel_tri(3) AND NOT demux_dsp_sel_tri(1));
imp_slp <= '0';
off_adj <= '0';
off_adj_delay <= '0';
FDCPE_post_sleep_BUFR: FDCPE port map (post_sleep_BUFR,post_sleep_BUFR_D,CLK,'0',reset,'1');
post_sleep_BUFR_D <= NOT (((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT post_sleep_BUFR)
OR (NOT N_PZ_4398 AND NOT post_sleep_BUFR)
OR (NOT N_PZ_4291 AND NOT post_sleep_BUFR)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND cntr_cnt(0) AND
N_PZ_4285 AND cntr_cnt(1) AND cntr_cnt(3) AND cntr_cnt(2) AND
NOT cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7))));
post_sleep <= post_sleep_BUFR;
FDCPE_pre_sleep: FDCPE port map (pre_sleep,pre_sleep_D,CLK,'0',reset,'1');
pre_sleep_D <= NOT ((NOT N_PZ_4127 AND NOT pre_sleep));
rb_pd_l <= '0';
rec_prot <= '0';
FDCPE_row_clk: FDCPE port map (row_clk,row_clk_D,CLK,reset,'0','1');
row_clk_D <= ((N_PZ_4126 AND row_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND row_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
row_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND row_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4299 AND row_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT N_PZ_4093 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5));
FTCPE_row_pulse_BUFR: FTCPE port map (row_pulse_BUFR,row_pulse_BUFR_T,CLK,reset,'0','1');
row_pulse_BUFR_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
row_pulse_BUFR)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT row_pulse_BUFR)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT row_pulse_BUFR));
row_pulse <= row_pulse_BUFR;
FTCPE_sample_reg_load: FTCPE port map (sample_reg_load,sample_reg_load_T,CLK,reset,'0','1');
sample_reg_load_T <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
sample_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
sample_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
N_PZ_4291 AND NOT sample_reg_load));
FTCPE_sel_clk: FTCPE port map (sel_clk,sel_clk_T,CLK,reset,'0','1');
sel_clk_T <= NOT (((N_PZ_4398 AND NOT sel_clk)
OR (N_PZ_4126 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4126 AND
sel_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT sel_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4126 AND
sel_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT sel_clk)
OR (N_PZ_4350 AND N_PZ_4299 AND N_PZ_4093)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
NOT N_PZ_4127 AND N_PZ_4126)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND NOT sel_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT sel_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4398 AND
NOT N_PZ_4093 AND sel_clk)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT N_PZ_4093 AND sel_clk)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt0 AND FSM/SHELL1_DSP_SM_2/row_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/row_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/row_cnt3)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4126 AND FSM/SHELL1_DSP_SM_2/sel_cnt0 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt2 AND NOT FSM/SHELL1_DSP_SM_2/sel_cnt1 AND
NOT FSM/SHELL1_DSP_SM_2/sel_cnt3)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND
FSM/SHELL1_DSP_SM_2/col_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt2 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt5)
OR (N_PZ_4285 AND N_PZ_4398 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5)));
FDCPE_sel_pulse: FDCPE port map (sel_pulse,sel_pulse_D,CLK,reset,'0','1');
sel_pulse_D <= ((NOT N_PZ_4398 AND sel_pulse)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4285 AND
sel_pulse)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4291 AND
sel_pulse)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4350 AND N_PZ_4208)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND N_PZ_4299)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND sel_pulse)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt0 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt1 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt2 AND
FSM/SHELL1_DSP_SM_2/ramp_cnt3 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt4 AND
NOT FSM/SHELL1_DSP_SM_2/ramp_cnt5 AND NOT FSM/SHELL1_DSP_SM_2/ramp_cnt6 AND sel_pulse));
FDCPE_status_reg_data0: FDCPE port map (status_reg_data(0),status_reg_data_D(0),CLK,reset,'0','1');
status_reg_data_D(0) <= ((N_PZ_4187 AND status_reg_data(0))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND status_reg_data(0))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
status_reg_data(0) AND N_PZ_4399)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
N_PZ_4291)
OR (N_PZ_4350 AND status_reg_data(0) AND N_PZ_4399)
OR (NOT N_PZ_4398 AND status_reg_data(0) AND N_PZ_4399)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4093 AND status_reg_data(0))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
status_reg_data(0))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND
N_PZ_4299 AND status_reg_data(0)));
FDCPE_status_reg_data1: FDCPE port map (status_reg_data(1),status_reg_data_D(1),CLK,reset,'0','1');
status_reg_data_D(1) <= ((N_PZ_4126 AND status_reg_data(1))
OR (N_PZ_4399 AND status_reg_data(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
status_reg_data(1))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4299 AND status_reg_data(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4291 AND status_reg_data(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
status_reg_data(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
status_reg_data(1))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4));
FTCPE_status_reg_data2: FTCPE port map (status_reg_data(2),status_reg_data_T(2),CLK,reset,'0','1');
status_reg_data_T(2) <= ((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
N_PZ_4291 AND NOT status_reg_data(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND NOT N_PZ_4398 AND NOT status_reg_data(2))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4398 AND NOT N_PZ_4283 AND NOT status_reg_data(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4398 AND
NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
NOT N_PZ_4299 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND status_reg_data(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT N_PZ_4187 AND
NOT N_PZ_4399 AND status_reg_data(2))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4285 AND NOT N_PZ_4398 AND NOT N_PZ_4187 AND NOT N_PZ_4399 AND
status_reg_data(2)));
FDCPE_status_reg_data3: FDCPE port map (status_reg_data(3),status_reg_data_D(3),CLK,reset,'0','1');
status_reg_data_D(3) <= NOT (((N_PZ_4126 AND NOT status_reg_data(3))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4398 AND
N_PZ_4291)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4350 AND NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND
NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT N_PZ_4398)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4398 AND
N_PZ_4299 AND NOT status_reg_data(3))
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT N_PZ_4398 AND
NOT N_PZ_4093 AND NOT status_reg_data(3))
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND N_PZ_4398 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT status_reg_data(3))));
FDCPE_status_reg_load: FDCPE port map (status_reg_load,status_reg_load_D,CLK,reset,'0','1');
status_reg_load_D <= NOT (((NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4126 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND N_PZ_4126 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4350 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT status_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND N_PZ_4350 AND
NOT N_PZ_4291 AND NOT status_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT status_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command1 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT FSM/SHELL1_DSP_SM_2/tochip_command0 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND NOT N_PZ_4187 AND
NOT status_reg_load)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND N_PZ_4299 AND
NOT status_reg_load)
OR (NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND N_PZ_4285 AND
NOT FSM/SHELL1_DSP_SM_2/col_cnt0 AND NOT FSM/SHELL1_DSP_SM_2/col_cnt1 AND
FSM/SHELL1_DSP_SM_2/col_cnt2 AND FSM/SHELL1_DSP_SM_2/col_cnt3 AND
FSM/SHELL1_DSP_SM_2/col_cnt4 AND FSM/SHELL1_DSP_SM_2/col_cnt5 AND NOT status_reg_load)));
LDCP_status_reg_load_out: LDCP port map (status_reg_load_out,status_reg_load_out_D,NOT ,'0','0');
status_reg_load_out_D <= (demux_dsp_sel_load(0) AND demux_dsp_sel_load(2) AND
NOT demux_dsp_sel_load(3) AND demux_dsp_sel_load(1));
FTCPE_transmit: FTCPE port map (transmit,transmit_T,CLK,reset,'0','1');
transmit_T <= ((FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd1 AND
FSM/SHELL1_DSP_SM_2/sreg_chip_FFd3 AND FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND transmit)
OR (FSM/SHELL1_DSP_SM_2/sreg_chip_FFd2 AND
NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd5 AND NOT FSM/SHELL1_DSP_SM_2/sreg_chip_FFd4 AND NOT cntr_cnt(0) AND
N_PZ_4285 AND NOT cntr_cnt(1) AND NOT cntr_cnt(3) AND cntr_cnt(2) AND
cntr_cnt(4) AND NOT cntr_cnt(5) AND NOT cntr_cnt(6) AND NOT cntr_cnt(7) AND
NOT transmit));
wr_clk_en <= '0';
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE);
FTCPE (Q,D,C,CLR,PRE,CE);
LDCP (Q,D,G,CLR,PRE);
****************************** Device Pin Out *****************************
Device : XCR3256XL-12-PQ208
Pin Signal Pin Signal
No. Name No. Name
1 NC 105 NC
2 NC 106 NC
3 dsp_data<0> 107 VCC
4 dsp_data<1> 108 WPU
5 VCC 109 dsp_data<25>
6 dsp_data<2> 110 dsp_data<26>
7 dsp_data<3> 111 dsp_data<27>
8 dsp_data<4> 112 dsp_data<28>
9 dsp_data<5> 113 dsp_data<29>
10 dsp_data<6> 114 dsp_data<30>
11 dsp_data<7> 115 dsp_data<31>
12 WPU 116 PE
13 WPU 117 dsp_add<0>
14 GND 118 dsp_add<1>
15 WPU 119 dsp_add<2>
16 WPU 120 dsp_add<3>
17 WPU 121 WPU
18 PRE 122 WPU
19 SAN 123 WPU
20 pre_sleep 124 WPU
21 imp_slp 125 VCC
22 post_sleep 126 dsp_data<24>
23 VCC 127 TMS
24 row_pulse 128 dsp_data<23>
25 row_clk 129 dsp_data<22>
26 col_clk 130 dsp_data<21>
27 sel_clk 131 dsp_data<20>
28 col_pulse 132 dsp_data<19>
29 sel_pulse 133 dsp_data<18>
30 TCK 134 GND
31 wr_clk_en 135 dsp_data<17>
32 GND 136 dsp_data<16>
33 comp_sleep 137 dsp_data<15>
34 SH_samp_0 138 dsp_data<14>
35 SH_samp_1 139 dsp_data<13>
36 SH_samp_2 140 dsp_data<12>
37 SH_samp_3 141 dsp_data<11>
38 VREG_EN_l 142 dsp_data<10>
39 WPU 143 VCC
40 WPU 144 dsp_data<9>
41 VCC 145 dsp_data<8>
42 WPU 146 dsp_awe_l
43 WPU 147 dsp_are_l
44 WPU 148 dsp_asm2_l
45 WPU 149 WPU
46 WPU 150 WPU
47 WPU 151 WPU
48 WPU 152 GND
49 WPU 153 WPU
50 GND 154 WPU
51 NC 155 NC
52 NC 156 NC
53 NC 157 NC
54 NC 158 NC
55 WPU 159 WPU
56 cntr_9 160 data<15>
57 cntr_8 161 data<14>
58 dac_en 162 data<13>
59 dac_pd 163 data<12>
60 dac_cs_l 164 data<11>
61 dac_clk 165 VCC
62 rb_pd_l 166 data<10>
63 VCC 167 data<9>
64 data<31> 168 data<8>
65 data<30> 169 chip_sel<5>
66 data<29> 170 chip_sel<6>
67 data<28> 171 chip_sel<3>
68 data<27> 172 chip_sel<4>
69 data<26> 173 chip_sel<1>
70 data<25> 174 GND
71 data<24> 175 chip_sel<2>
72 GND 176 TDI
73 data<23> 177 WPU
74 VCC 178 WPU
75 GND 179 VCC
76 data<22> 180 GND
77 data<21> 181 CLK
78 chip_sel<12> 182 TIE
79 chip_sel<11> 183 TIE
80 chip_sel<10> 184 TIE
81 chip_sel<9> 185 GND
82 GND 186 VCC
83 VCC 187 WPU
84 chip_sel<8> 188 WPU
85 VCC 189 TDO
86 chip_sel<7> 190 WPU
87 data<20> 191 VCC
88 data<19> 192 data<7>
89 data<18> 193 data<6>
90 data<17> 194 data<5>
91 data<16> 195 data<4>
92 off_adj 196 data<3>
93 off_adj_delay 197 data<2>
94 GND 198 data<1>
95 WPU 199 data<0>
96 reset 200 GND
97 transmit 201 WPU
98 WPU 202 WPU
99 WPU 203 WPU
100 status_reg_load_out 204 WPU
101 fake_transmit 205 WPU
102 rec_prot 206 WPU
103 NC 207 NC
104 NC 208 NC
Legend : NC = Not Connected, unbonded pin
PE = Port Enable pin
WPU = Unused with Internal Weak Pull Up
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : xcr3256xl-12-PQ208
Optimization Method : DENSITY
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : ON
Keep Unused Inputs : OFF
Slew Rate : FAST
Set Unused I/O Pin Termination : PULLUP
Set Input-Only Termination : FLOAT
Set Universal Control Term Optimization : OFF
Enable Foldback NANDs : OFF
Reserve ISP Pins : ON
Enable Input Registers : ON
Function Block Fan-in Limit : 38
Input Limit : 28
Pterm Limit : 28